| #
29ba22e8 |
| 12-Mar-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(security): workaround for CVE-2022-23960" into integration
|
| #
1fe4a9d1 |
| 18-Jan-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(security): workaround for CVE-2022-23960
Implements the loop workaround for Cortex-A77, Cortex-A78,
Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1
CPUs.
Signed-off-by: Bipin R
fix(security): workaround for CVE-2022-23960
Implements the loop workaround for Cortex-A77, Cortex-A78,
Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1
CPUs.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
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| #
337e4933 |
| 14-Jan-2021 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes I36e4d672,I47610cee into integration
* changes:
Workaround for Cortex N1 erratum 1946160
Workaround for Cortex A78 erratum 1951500
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| #
263ee781 |
| 07-Oct-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex N1 erratum 1946160
Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST
before acquire at
Workaround for Cortex N1 erratum 1946160
Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST
before acquire atomic instructions without release semantics. This
issue is present starting from r0p0 but this workaround applies to
revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no
workaround.
SDEN can be found here:
https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
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| #
9dd2896e |
| 01-Dec-2020 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "Add support for Neoverse-N2 CPUs." into integration
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| #
25bbbd2d |
| 23-Oct-2020 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8
Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
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| #
238db174 |
| 11-Sep-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Workaround for Neoverse N1 erratum 1868343" into integration
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| #
61f0ffc4 |
| 05-Aug-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Neoverse N1 erratum 1868343
Neoverse N1 erratum 1868343 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core. The workaround is to
set a bit in the CPUACT
Workaround for Neoverse N1 erratum 1868343
Neoverse N1 erratum 1868343 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core. The workaround is to
set a bit in the CPUACTLR_EL1 system register, which delays instruction
fetch after branch misprediction. This workaround will have a small
impact on performance.
SDEN can be found here:
https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844
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| #
7ef3e0b3 |
| 03-Sep-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "lib: cpu: Check SCU presence in DSU before accessing DSU registers" into integration
|
| #
942013e1 |
| 05-Feb-2020 |
Pramod Kumar <pramod.kumar@broadcom.com> |
lib: cpu: Check SCU presence in DSU before accessing DSU registers
The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT"
lib: cpu: Check SCU presence in DSU before accessing DSU registers
The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT" L3
memory system variant is used, there won't be any L3 cache,
snoop filter, and SCU logic present hence no system control register
will be present. Hence check SCU presence before accessing DSU register
for DSU_936184 errata.
Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Change-Id: I1ffa8afb0447ae3bd1032c9dd678d68021fe5a63
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| #
1056ddce |
| 23-Jul-2020 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "Revert workaround for Neoverse N1 erratum 1800710" into integration
|
| #
f0bbaebc |
| 23-Jul-2020 |
johpow01 <john.powell@arm.com> |
Revert workaround for Neoverse N1 erratum 1800710
This reverts commit 11af40b6308ac75c83e874129bb79bc3a58060bf, reversing
changes made to 2afcf1d4b845272791b75c8285108c4dcd91e2b9.
This errata worka
Revert workaround for Neoverse N1 erratum 1800710
This reverts commit 11af40b6308ac75c83e874129bb79bc3a58060bf, reversing
changes made to 2afcf1d4b845272791b75c8285108c4dcd91e2b9.
This errata workaround did not work as intended so we are reverting this
change. In the future, when the corrected workaround is published in an
SDEN, we will push a new workaround.
This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4750
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I20aa064c1bac9671939e657bec269d32b9e75a97
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| #
11af40b6 |
| 01-Jul-2020 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "Workaround for Neoverse N1 erratum 1800710" into integration
|
| #
0e0521bd |
| 02-Jun-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Neoverse N1 erratum 1800710
Neoverse N1 erratum 1800710 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core. The workaround is to
set a bit in the ECTLR_
Workaround for Neoverse N1 erratum 1800710
Neoverse N1 erratum 1800710 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core. The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.
This errata is explained in this SDEN:
https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6
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| #
91ff490d |
| 28-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Neovers N1: added support to update presence of External LLC" into integration
|
| #
f2d6b4ee |
| 24-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal L
Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal LLC.
To cater for the platforms(like N1SDP) which has external LLC present
introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be
enabled by platform port.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
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| #
5f3ed6aa |
| 24-Jan-2020 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Prevent speculative execution past ERET" into integration
|
| #
f461fe34 |
| 07-Jan-2020 |
Anthony Steinhauser <asteinhauser@google.com> |
Prevent speculative execution past ERET
Even though ERET always causes a jump to another address, aarch64 CPUs
speculatively execute following instructions as if the ERET
instruction was not a jump
Prevent speculative execution past ERET
Even though ERET always causes a jump to another address, aarch64 CPUs
speculatively execute following instructions as if the ERET
instruction was not a jump instruction.
The speculative execution does not cross privilege-levels (to the jump
target as one would expect), but it continues on the kernel privilege
level as if the ERET instruction did not change the control flow -
thus execution anything that is accidentally linked after the ERET
instruction. Later, the results of this speculative execution are
always architecturally discarded, however they can leak data using
microarchitectural side channels. This speculative execution is very
reliable (seems to be unconditional) and it manages to complete even
relatively performance-heavy operations (e.g. multiple dependent
fetches from uncached memory).
This was fixed in Linux, FreeBSD, OpenBSD and Optee OS:
https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8
https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61
https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2
https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a
It is demonstrated in a SafeSide example:
https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc
https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c
Signed-off-by: Anthony Steinhauser <asteinhauser@google.com>
Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
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| #
0efb83e1 |
| 13-Nov-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "Fix white space errors + remove #if defined" into integration
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| #
22cab650 |
| 11-Oct-2019 |
laurenw-arm <lauren.wehrmeister@arm.com> |
Fix white space errors + remove #if defined
Fix a few white space errors and remove #if defined in workaround
for N1 Errata 1542419.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
C
Fix white space errors + remove #if defined
Fix a few white space errors and remove #if defined in workaround
for N1 Errata 1542419.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I07ac5a2fd50cd63de53c06e3d0f8262871b62fad
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|
| #
25792ce4 |
| 07-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Neoverse N1 Errata Workaround 1542419" into integration
|
| #
80942622 |
| 20-Aug-2019 |
laurenw-arm <lauren.wehrmeister@arm.com> |
Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instr
Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.
The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
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|
| #
75cfba10 |
| 20-Aug-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "Fix for N1 1043202 Errata Workaround" into integration
|
| #
a33ec1e7 |
| 19-Aug-2019 |
laurenw-arm <lauren.wehrmeister@arm.com> |
Fix for N1 1043202 Errata Workaround
ISB instruction was removed from the N1 1043202 Errata Workaround [1], this
fix is adding the ISB instruction back in.
[1] http://infocenter.arm.com/help/index.
Fix for N1 1043202 Errata Workaround
ISB instruction was removed from the N1 1043202 Errata Workaround [1], this
fix is adding the ISB instruction back in.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I74eac7f6ad38991c36d423ad6aa44558033ad388
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| #
bb2d778c |
| 04-Jul-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "lw/n1_errata_fixes" into integration
* changes:
Removing redundant ISB instructions
Workaround for Neoverse N1 erratum 1275112
Workaround for Neoverse N1 erratum 1262
Merge changes from topic "lw/n1_errata_fixes" into integration
* changes:
Removing redundant ISB instructions
Workaround for Neoverse N1 erratum 1275112
Workaround for Neoverse N1 erratum 1262888
Workaround for Neoverse N1 erratum 1262606
Workaround for Neoverse N1 erratum 1257314
Workaround for Neoverse N1 erratum 1220197
Workaround for Neoverse N1 erratum 1207823
Workaround for Neoverse N1 erratum 1165347
Workaround for Neoverse N1 erratum 1130799
Workaround for Neoverse N1 erratum 1073348
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|