lib: cpus: aarch32: sanity check pointers before use

This is the AARCH32 update of patch [1].

[1] 601e3ed209eb ("lib: cpus: sanity check pointers before use")

Signed-off-by: Yann Gautier <yann.ga

lib: cpus: aarch32: sanity check pointers before use

This is the AARCH32 update of patch [1].

[1] 601e3ed209eb ("lib: cpus: sanity check pointers before use")

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I43dbe00a5802a7e1c6f877e22d1c66ec8275c6fa

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Cortex A9:errata 794073 workaround

On Cortex A9 an errata can cause the processor to violate the rules for
speculative fetches when the MMU is off but branch prediction has not
been disabled. The wo

Cortex A9:errata 794073 workaround

On Cortex A9 an errata can cause the processor to violate the rules for
speculative fetches when the MMU is off but branch prediction has not
been disabled. The workaround for this is to execute an Invalidate
Entire Branch Prediction Array (BPIALL) followed by a DSB.

see:http://arminfo.emea.arm.com/help/topic/com.arm.doc.uan0009d/UAN0009_cortex_a9_errata_r4.pdf
for more details.

Change-Id: I9146c1fa7563a79f4e15b6251617b9620a587c93
Signed-off-by: Joel Hutton <Joel.Hutton@arm.com>

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Cortex-A17: Implement workaround for errata 852423

Change-Id: I3a101e540f0b134ecf9a51fa3d7d8e3d0369b297
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Cortex-A17: Implement workaround for errata 852421

Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Cortex-A15: Implement workaround for errata 827671

This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].

[1]

Cortex-A15: Implement workaround for errata 827671

This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html

Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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Cortex-A15: Implement workaround for errata 816470

Change-Id: I9755252725be25bfd0147839d7df56888424ff84
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Fixup register handling in aarch32 reset_handler

The BL handover interface stores the bootloader arguments in
registers r9-r12, so when the reset_handler stores the lr pointer
in r10 it clobers one

Fixup register handling in aarch32 reset_handler

The BL handover interface stores the bootloader arguments in
registers r9-r12, so when the reset_handler stores the lr pointer
in r10 it clobers one of the arguments.

Adapt to use r8 and adapt the comment about registers allowed
to clober.

I've checked aarch32 reset_handlers and none seem to use higher
registers as far as I can tell.

Fixes: a6f340fe58b9 ("Introduce the new BL handover interface")
Cc: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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Merge pull request #1751 from vwadekar/tegra-scatter-file-support

Tegra scatter file support

Cortex-A53: Workarounds for 819472, 824069 and 827319

The workarounds for these errata are so closely related that it is
better to only have one patch to make it easier to understand.

Change-Id: I0

Cortex-A53: Workarounds for 819472, 824069 and 827319

The workarounds for these errata are so closely related that it is
better to only have one patch to make it easier to understand.

Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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Cortex-A57: Implement workaround for erratum 817169

Change-Id: I25f29a275ecccd7d0c9d33906e6c85967caa767a
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Cortex-A57: Implement workaround for erratum 814670

Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Tegra: Support for scatterfile for the BL31 image

This patch provides support for using the scatterfile format as
the linker script with the 'armlink' linker for Tegra platforms.

In order to enable

Tegra: Support for scatterfile for the BL31 image

This patch provides support for using the scatterfile format as
the linker script with the 'armlink' linker for Tegra platforms.

In order to enable the scatterfile usage the following changes
have been made:

* provide mapping for ld.S symbols in bl_common.h
* include bl_common.h from all the affected files
* update the makefile rules to use the scatterfile and armlink
to compile BL31
* update pubsub.h to add sections to the scatterfile

NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY.

Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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