feat(arm): ecdsa p384/p256 full key support

Add full key support for ECDSA P384 and P256.

New .S files and p384 pem file created along with new
plat_get_rotpk_info() flag ARM_ROTPK_DEVEL_FULL_DEV_E

feat(arm): ecdsa p384/p256 full key support

Add full key support for ECDSA P384 and P256.

New .S files and p384 pem file created along with new
plat_get_rotpk_info() flag ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID.

Change-Id: I578b257eca41070bb4f4791ef429f2b8a66b1eb3
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Merge "fix: bl2 start address for RESET_TO_BL2+ENABLE_PIE" into integration

fix: bl2 start address for RESET_TO_BL2+ENABLE_PIE

BL31 image has grown with feature addition over time. In particular the
RESET_TO_BL2 + ENABLE_PIE + DEBUG combination of options lead to BL31
image

fix: bl2 start address for RESET_TO_BL2+ENABLE_PIE

BL31 image has grown with feature addition over time. In particular the
RESET_TO_BL2 + ENABLE_PIE + DEBUG combination of options lead to BL31
image overlap head of BL2 image. In this configuration BL2 is meant to
stay resident as PE reset occurs from BL2. Apply changes similar to [1]
such that BL2 start address is pushed forward and leaves more room for
BL31 end of image.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/15486/9/include/plat/arm/common/arm_def.h#530

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I027e23780fb77ca9fe81aa47231da649c7a030ee

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Merge changes from topic "CPU_RAS_FF" into integration

* changes:
feat(rdn2): enable Neoverse N2 CPU error handling support
feat(sgi): firmware first error handling for Neoverse N2 CPU
feat(ar

Merge changes from topic "CPU_RAS_FF" into integration

* changes:
feat(rdn2): enable Neoverse N2 CPU error handling support
feat(sgi): firmware first error handling for Neoverse N2 CPU
feat(arm): enable FHI PPI interrupt to report CPU errors

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feat(arm): enable FHI PPI interrupt to report CPU errors

To handle the core corrected errors in the firmware, the FHI PPI
interrupt has to be enabled on all the cores. At boot, when the RAS
framewor

feat(arm): enable FHI PPI interrupt to report CPU errors

To handle the core corrected errors in the firmware, the FHI PPI
interrupt has to be enabled on all the cores. At boot, when the RAS
framework is initialized, only primary core is up and hence core FHI PPI
interrupt is enabled only on primary core. This patch adds support to
configure and enable core FHI interrupt for all the secondary cores as
part of their boot sequence.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I4b25152cb498fe975b9c770babb25aa9e01f9656

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Merge "fix(fvp): adjust BL31 maximum size as per total SRAM size" into integration

fix(fvp): adjust BL31 maximum size as per total SRAM size

Adjusted BL31 maximum size as per total SRAM size.

Change-Id: Ifdfdedb8af3e001cebba8e60c973f3c72be11652
Signed-off-by: Manish V Badarkhe <M

fix(fvp): adjust BL31 maximum size as per total SRAM size

Adjusted BL31 maximum size as per total SRAM size.

Change-Id: Ifdfdedb8af3e001cebba8e60c973f3c72be11652
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes from topic "RAS_REFACTORING" into integration

* changes:
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
feat(plat/arm): add memory map entry for CPER memor

Merge changes from topic "RAS_REFACTORING" into integration

* changes:
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
feat(plat/arm): add memory map entry for CPER memory region
feat(plat/arm): firmware first error handling support for base RAMs
feat(plat/arm): update common platform RAS implementation
feat(plat/sgi): remove RAS setup call from common code
refactor(plat/sgi): deprecate DMC-620 RAS support
fix(plat/common): register PLAT_SP_PRI only if not already registered
fix(plat/sgi): update PLAT_SP_PRI macro definition
fix(plat/arm): add RAS_FFH_SUPPORT check for RAS EHF priority

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fix(plat/arm): add RAS_FFH_SUPPORT check for RAS EHF priority

Define RAS EHF priority only if RAS_FFH_SUPPORT is enabled.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I01

fix(plat/arm): add RAS_FFH_SUPPORT check for RAS EHF priority

Define RAS EHF priority only if RAS_FFH_SUPPORT is enabled.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I0183a0af510337c8dfb9d12427541fa6c91bb4a5

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Merge "fix: increase BL32 limit" into integration

fix: increase BL32 limit

BL32_LIMIT has been increased from 2MB to 4MB to accommodate
the latest tee.bin (it is around ~2.1MB).

Change-Id: I47b770bf23c23d38931a2b3316d076b829338d70
Signed-off-by: M

fix: increase BL32 limit

BL32_LIMIT has been increased from 2MB to 4MB to accommodate
the latest tee.bin (it is around ~2.1MB).

Change-Id: I47b770bf23c23d38931a2b3316d076b829338d70
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Co-developed-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge changes from topic "mb/secure-evlog-cpy" into integration

* changes:
feat(fvp): copy the Event Log to TZC secured DRAM area
feat(arm): carveout DRAM1 area for Event Log

Merge "refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3" into integration

refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3

BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is runnin

refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3

BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).

BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.

Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>

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feat(arm): carveout DRAM1 area for Event Log

Reserved 4KB area for Event Log in DRAM1. This area is used by BL2
to copy Event Log from internal SRAM to this carved out DRAM region
in the subsequent

feat(arm): carveout DRAM1 area for Event Log

Reserved 4KB area for Event Log in DRAM1. This area is used by BL2
to copy Event Log from internal SRAM to this carved out DRAM region
in the subsequent patch.

Change-Id: I7b405775c66d249e31edf7688d95770e6c05c175
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes I51c13c52,I3358c51e into integration

* changes:
build: always prefix section names with `.`
build: communicate correct page size to linker

build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section name

build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be
difficult to select in linker scripts when there is a lack of a
delimiter.

This change introduces the period prefix to all specialized section
names.

BREAKING-CHANGE: All input and output linker section names have been
prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.

Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes I1b092bc1,Ifc2461b4,I5176caa5 into integration

* changes:
docs(rme): update RMM-EL3 Boot Manifest structure description
feat(rme): read DRAM information from FVP DTB
feat(rme): s

Merge changes I1b092bc1,Ifc2461b4,I5176caa5 into integration

* changes:
docs(rme): update RMM-EL3 Boot Manifest structure description
feat(rme): read DRAM information from FVP DTB
feat(rme): set DRAM information in Boot Manifest platform data

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feat(rme): read DRAM information from FVP DTB

This patch builds on the previous patch by implementing
support for reading NS DRAM layout of FVP model from
HW_CONFIG Device tree.

Macro _RMMD_MANIFES

feat(rme): read DRAM information from FVP DTB

This patch builds on the previous patch by implementing
support for reading NS DRAM layout of FVP model from
HW_CONFIG Device tree.

Macro _RMMD_MANIFEST_VERSION is renamed to
SET_RMMD_MANIFEST_VERSION to suppress MISRA-C
"rule MC3R1.D4.5: (advisory) Identifiers in
the same name space with overlapping visibility
should be typographically unambiguous" warning

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: Ifc2461b4441a1efdd4b7c656ab4d15e62479f77b

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feat(rme): set DRAM information in Boot Manifest platform data

This patch adds support for setting configuration of DRAM banks
for FVP model in RMM-EL3 Boot Manifest structure.
Structure 'rmm_manife

feat(rme): set DRAM information in Boot Manifest platform data

This patch adds support for setting configuration of DRAM banks
for FVP model in RMM-EL3 Boot Manifest structure.
Structure 'rmm_manifest' is extended with 'plat_dram' structure
which contains information about platform's DRAM layout:
- number of DRAM banks;
- pointer to 'dram_bank[]' array;
- check sum: two's complement 64-bit value of the sum of
data in 'plat_dram' and 'dram_bank[] array.
Each 'dram_bank' structure holds information about DRAM
bank base address and its size. This values must be aligned
to 4KB page size.
The patch increases Boot Manifest minor version to 2 and
removes 'typedef rmm_manifest_t' as per
"3.4.15.1. Avoid anonymous typedefs of structs/enums in headers" of
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I5176caa5780e27d1e0daeb5dea3e40cf6ad5fd12

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Merge changes from topic "full_dev_rsa_key" into integration

* changes:
docs(arm): add ARM_ROTPK_LOCATION variant full key
feat(arm): add ARM_ROTPK_LOCATION variant full key

feat(arm): add ARM_ROTPK_LOCATION variant full key

Add support for ARM_ROTPK_LOCATION=devel_full_dev_rsa_key, which
implements the scenario where the platform provides the full ROTPK, as
opposed to

feat(arm): add ARM_ROTPK_LOCATION variant full key

Add support for ARM_ROTPK_LOCATION=devel_full_dev_rsa_key, which
implements the scenario where the platform provides the full ROTPK, as
opposed to the hash of it. This returns a 2kB development RSA key
embedded into the firmware.

The motivation for this patch is to extend our test coverage in the CI.
Right now, the authentication framework allows platforms to return
either the full ROTPK or a hash of it (*). However, the FVP platform
only supports returning a hash currently so we cannot easily exercise
the full key scenario. This patch adds that capability.

(*) Or even no key at all if it's not deployed on the platform yet, as
is typically the case on pre-production/developement platforms.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ie869cca1082410e63894e2b7dea2d31155684105

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Merge "fix(rme): xlat table setup fails for bl2" into integration

fix(rme): xlat table setup fails for bl2

The patch 8c980a4 created a 4KB shared region from the 32MB
Realm region for RMM-EL3 communication. But this meant that BL2
needs to map a region of 32MB - 4

fix(rme): xlat table setup fails for bl2

The patch 8c980a4 created a 4KB shared region from the 32MB
Realm region for RMM-EL3 communication. But this meant that BL2
needs to map a region of 32MB - 4KB, which required more xlat
tables at runtime. This patch maps the entire 32MB region in BL2
which is more memory efficient in terms of xlat tables needed.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I17aa27545293d7b5bbec1c9132ea2c22bf2e7e65

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Merge changes from topic "jas/rmm-el3-ifc" into integration

* changes:
docs(rmmd): document EL3-RMM Interfaces
feat(rmmd): add support to create a boot manifest
fix(rme): use RMM shared buffer

Merge changes from topic "jas/rmm-el3-ifc" into integration

* changes:
docs(rmmd): document EL3-RMM Interfaces
feat(rmmd): add support to create a boot manifest
fix(rme): use RMM shared buffer for attest SMCs
feat(rmmd): add support for RMM Boot interface

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