feat(spmc): add support for v1.1 FF-A memory data structures

Add support for the FF-A v1.1 data structures to the EL3 SPMC
and enable the ability to convert between v1.0 and the v1.1
forwards compat

feat(spmc): add support for v1.1 FF-A memory data structures

Add support for the FF-A v1.1 data structures to the EL3 SPMC
and enable the ability to convert between v1.0 and the v1.1
forwards compatible data structures.

The SPMC now uses the v1.1 data structures internally and will
convert descriptors as required depending on the FF-A version
supported by the calling partition.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ic14a95ea2e49c989aecf19b927a6b21ac50f863e

show more ...

Merge changes I500ddbe9,I9c10dac9,I53bfff85,I06f7594d,I24bff8d4, ... into integration

* changes:
nxp lx2160a-aqds: new plat based on soc lx2160a
NXP lx2160a-rdb: new plat based on SoC lx2160a

Merge changes I500ddbe9,I9c10dac9,I53bfff85,I06f7594d,I24bff8d4, ... into integration

* changes:
nxp lx2160a-aqds: new plat based on soc lx2160a
NXP lx2160a-rdb: new plat based on SoC lx2160a
nxp lx2162aqds: new plat based on soc lx2160a
nxp: errata handling at soc level for lx2160a
nxp: make file for loading additional ddr image
nxp: adding support of soc lx2160a
nxp: deflt hdr files for soc & their platforms
nxp: platform files for bl2 and bl31 setup
nxp: warm reset support to retain ddr content
nxp: nv storage api on platforms
nxp: supports two mode of trusted board boot
nxp: fip-handler for additional fip_fuse.bin
nxp: fip-handler for additional ddr-fip.bin
nxp: image loader for loading fip image
nxp: svp & sip smc handling
nxp: psci platform functions used by lib/psci
nxp: helper function used by plat & common code
nxp: add data handler used by bl31
nxp: adding the driver.mk file
nxp-tool: for creating pbl file from bl2
nxp: adding the smmu driver
nxp: cot using nxp internal and mbedtls
nxp:driver for crypto h/w accelerator caam
nxp:add driver support for sd and emmc
nxp:add qspi driver
nxp: add flexspi driver support
nxp: adding gic apis for nxp soc
nxp: gpio driver support
nxp: added csu driver
nxp: driver pmu for nxp soc
nxp: ddr driver enablement for nxp layerscape soc
nxp: i2c driver support.
NXP: Driver for NXP Security Monitor
NXP: SFP driver support for NXP SoC
NXP: Interconnect API based on ARM CCN-CCI driver
NXP: TZC API to configure ddr region
NXP: Timer API added to enable ARM generic timer
nxp: add dcfg driver
nxp:add console driver for nxp platform
tools: add mechanism to allow platform specific image UUID
tbbr-cot: conditional definition for the macro
tbbr-cot: fix the issue of compiling time define
cert_create: updated tool for platform defined certs, keys & extensions
tbbr-tools: enable override TRUSTED_KEY_CERT

show more ...

NXP: Timer API added to enable ARM generic timer

NXP Timer Apis are based on:
- drivers/delay_timer

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cbccf4c082a10affee1143390905b9cc9

NXP: Timer API added to enable ARM generic timer

NXP Timer Apis are based on:
- drivers/delay_timer

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cbccf4c082a10affee1143390905b9cc99c3382

show more ...

Merge "Fix MISRA C issues in BL1/BL2/BL31" into integration

Fix MISRA C issues in BL1/BL2/BL31

Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code.
Mainly issues like not using boolean expressions in conditionals,
conflicting variable name

Fix MISRA C issues in BL1/BL2/BL31

Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code.
Mainly issues like not using boolean expressions in conditionals,
conflicting variable names, ignoring return values without (void), adding
explicit casts, etc.

Change-Id: If1fa18ab621b9c374db73fa6eaa6f6e5e55c146a
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

Merge changes from topic "tegra-downstream-02092020" into integration

* changes:
Tegra: spe: uninit console on a timeout
Tegra: handler to check support for System Suspend
Tegra: bpmp_ipc: imp

Merge changes from topic "tegra-downstream-02092020" into integration

* changes:
Tegra: spe: uninit console on a timeout
Tegra: handler to check support for System Suspend
Tegra: bpmp_ipc: improve cyclomatic complexity
Tegra: platform handler to relocate BL32 image
Tegra: common: improve cyclomatic complexity
Tegra210: secure PMC hardware block
Tegra: delay_timer: support for physical secure timer
include: move MHZ_TICKS_PER_SEC to utils_def.h
Tegra194: memctrl: lock mc stream id security config
Tegra210: resume PMC hardware block for all platforms
Tegra: macro for legacy WDT FIQ handling
Tegra186: enable higher performance non-cacheable load forwarding
Tegra210: enable higher performance non-cacheable load forwarding
cpus: higher performance non-cacheable load forwarding

show more ...

include: move MHZ_TICKS_PER_SEC to utils_def.h

This patch moves the MHZ_TICKS_PER_SEC macro to utils_def.h
for other platforms to use.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id:

include: move MHZ_TICKS_PER_SEC to utils_def.h

This patch moves the MHZ_TICKS_PER_SEC macro to utils_def.h
for other platforms to use.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I6c4dc733f548d73cfdb3515ec9ad89a9efaf4407

show more ...

Merge changes from topic "ld/mtd_framework" into integration

* changes:
doc: stm32mp1: Update build command line
fdts: stm32mp1: remove second QSPI flash instance
stm32mp1: Add support for SPI

Merge changes from topic "ld/mtd_framework" into integration

* changes:
doc: stm32mp1: Update build command line
fdts: stm32mp1: remove second QSPI flash instance
stm32mp1: Add support for SPI-NOR boot device
stm32mp1: Add support for SPI-NAND boot device
spi: stm32_qspi: Add QSPI support
fdts: stm32mp1: update for FMC2 pin muxing
stm32mp1: Add support for raw NAND boot device
fmc: stm32_fmc2_nand: Add FMC2 driver support
stm32mp1: Reduce MAX_XLAT_TABLES to 4
io: stm32image: fix device_size type
stm32mp: add DT helper for reg by name
stm32mp1: add compilation flags for boot devices
lib: utils_def: add CLAMP macro
compiler_rt: Import popcountdi2.c and popcountsi2.c files
Add SPI-NOR framework
Add SPI-NAND framework
Add SPI-MEM framework
Add raw NAND framework

show more ...

lib: utils_def: add CLAMP macro

Add the standard CLAMP macro. It ensures that
x is between the limits set by low and high.
If low is greater than high the result is undefined.

Signed-off-by: Lione

lib: utils_def: add CLAMP macro

Add the standard CLAMP macro. It ensures that
x is between the limits set by low and high.
If low is greater than high the result is undefined.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Ia173bb9ca51bc8d9a8ec573bbc15636a94f881f4

show more ...

Merge "Switch AARCH32/AARCH64 to __aarch64__" into integration

Merge "Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__" into integration

Switch AARCH32/AARCH64 to __aarch64__

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the cod

Switch AARCH32/AARCH64 to __aarch64__

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)

Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>

show more ...

Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__

NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.

All common C compilers predefine a macro called __ASSEMBLER__ when
pre

Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__

NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.

All common C compilers predefine a macro called __ASSEMBLER__ when
preprocessing a .S file. There is no reason for TF-A to define it's own
__ASSEMBLY__ macro for this purpose instead. To unify code with the
export headers (which use __ASSEMBLER__ to avoid one extra dependency),
let's deprecate __ASSEMBLY__ and switch the code base over to the
predefined standard.

Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417
Signed-off-by: Julius Werner <jwerner@chromium.org>

show more ...

Merge changes I0d17ba6c,I540741d2,I9e6475ad,Ifd769320,I12c04a85, ... into integration

* changes:
plat/mediatek/mt81*: Use new bl31_params_parse() helper
plat/rockchip: Use new bl31_params_parse_

Merge changes I0d17ba6c,I540741d2,I9e6475ad,Ifd769320,I12c04a85, ... into integration

* changes:
plat/mediatek/mt81*: Use new bl31_params_parse() helper
plat/rockchip: Use new bl31_params_parse_helper()
Add helper to parse BL31 parameters (both versions)
Factor out cross-BL API into export headers suitable for 3rd party code
Use explicit-width data types in AAPCS parameter structs
plat/rockchip: Switch to use new common BL aux parameter library
Introduce lightweight BL platform parameter library

show more ...

Factor out cross-BL API into export headers suitable for 3rd party code

This patch adds a new include/export/ directory meant for inclusion in
third-party code. This is useful for cases where third-

Factor out cross-BL API into export headers suitable for 3rd party code

This patch adds a new include/export/ directory meant for inclusion in
third-party code. This is useful for cases where third-party code needs
to interact with TF-A interfaces and data structures (such as a custom
BL2-implementation like coreboot handing off to BL31). Directly
including headers from the TF-A repository avoids having to duplicate
all these definitions (and risk them going stale), but with the current
header structure this is not possible because handoff API definitions
are too deeply intertwined with other TF code/headers and chain-include
other headers that will not be available in the other environment.

The new approach aims to solve this by separating only the parts that
are really needed into these special headers that are self-contained and
will not chain-include other (non-export) headers. TF-A code should
never include them directly but should instead always include the
respective wrapper header, which will include the required prerequisites
(like <stdint.h>) before including the export header. Third-party code
can include the export headers via its own wrappers that make sure the
necessary definitions are available in whatever way that environment can
provide them.

Change-Id: Ifd769320ba51371439a8e5dd5b79c2516c3b43ab
Signed-off-by: Julius Werner <jwerner@chromium.org>

show more ...

Merge pull request #1688 from JoelHutton/jh/variant_1_mitigations

Initial Spectre V1 mitigations (CVE-2017-5753).

Initial Spectre V1 mitigations (CVE-2017-5753).

Initial Spectre Variant 1 mitigations (CVE-2017-5753).
A potential speculative data leak was found in PSCI code, this depends
on a non-robust implemen

Initial Spectre V1 mitigations (CVE-2017-5753).

Initial Spectre Variant 1 mitigations (CVE-2017-5753).
A potential speculative data leak was found in PSCI code, this depends
on a non-robust implementation of the `plat_get_core_pos_by_mpidr()`
function. This is considered very low-risk. This patch adds a macro to
mitigate this. Note not all code paths could be analyzed with current
tools.

Add a macro which makes a variable 'speculation safe', using the
__builtin_speculation_safe_value function of GCC and llvm. This will be
available in GCC 9, and is planned for llvm, but is not currently in
mainline GCC or llvm. In order to implement this mitigation the compiler
must support this builtin. Support is indicated by the
__HAVE_SPECULATION_SAFE_VALUE flag.

The -mtrack-speculation option maintains a 'tracker' register, which
determines if the processor is in false speculation at any point. This
adds instructions and increases code size, but avoids the performance
impact of a hard barrier.

Without the -mtrack-speculation option, __builtin_speculation_safe_value
expands to a

ISB
DSB SY

sequence after a conditional branch, before the
speculation safe variable is used. With -mtrack-speculation a

CSEL tracker, tracker, XZR, [cond];
AND safeval,tracker;
CSDB

sequence is added instead, clearing the vulnerable variable by
AND'ing it with the tracker register, which is zero during speculative
execution. [cond] are the status flags which will only be true during
speculative execution. For more information on
__builtin_speculation_safe_value and the -mtrack-speculation option see
https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/compiler-support-for-mitigations

The -mtracking option was not added, as the performance impact of the
mitigation is low, and there is only one occurence.

Change-Id: Ic9e66d1f4a5155e42e3e4055594974c230bfba3c
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>

show more ...

Merge pull request #1697 from antonio-nino-diaz-arm/an/arch

Synchronise arch.h and arch_helpers.h with TF-A-Tests

Synchronise arch.h and arch_helpers.h with TF-A-Tests

The headers forked at some point in the past and have diverged a lot. In
order to make it easier to share code between TF-A-Tests and TF-A, this

Synchronise arch.h and arch_helpers.h with TF-A-Tests

The headers forked at some point in the past and have diverged a lot. In
order to make it easier to share code between TF-A-Tests and TF-A, this
patch synchronises most of the definitions in the mentioned headers.

This is not a complete sync, it has to be followed by more cleanup.

This patch also removes the read helpers for the AArch32 instructions
ats1cpr and ats1hr (they are write-only).

Change-Id: Id13ecd7aeb83bd2318cd47156d71a42f1c9f6ba2
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

show more ...

Merge pull request #1683 from Yann-lms/stm32mp1_multi_console

Add multi console support for STM32MP1

utils_def: add an assembly version for GENMASK

When compiling assembly files, stdint.h is not included.
UINT32_C and UINT64_C are then not defined.
A new GENMASK macro for assembly is then created.

utils_def: add an assembly version for GENMASK

When compiling assembly files, stdint.h is not included.
UINT32_C and UINT64_C are then not defined.
A new GENMASK macro for assembly is then created.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

show more ...

Merge pull request #1588 from satheesbalya-arm/sb1_2596_misra_tim_console

Fix misra warnings in delay timer and console drivers

Fix misra warnings in delay timer and console drivers

Change-Id: I43d2b3a0f672b4902edec3d3a39ffedbb0a701a3
Signed-off-by: Sathees Balya <sathees.balya@arm.com>

Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra

Fix several MISRA defects in PSCI library

Fix check_[uptr/u32]_overflow() macros MISRA defects

Add missing parentheses to fix MISRA C-2012 Rule 12.1.

Also, the result of a comparison is an essentially boolean value, it
isn't needed to retu

Fix check_[uptr/u32]_overflow() macros MISRA defects

Add missing parentheses to fix MISRA C-2012 Rule 12.1.

Also, the result of a comparison is an essentially boolean value, it
isn't needed to return 1 or 0 depending on it.

Also, fix header guards (MISRA C-2012 Rule 21.1).

Change-Id: I90c0bcdeb2787c1ca659fc9a981808ece7958de3
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

show more ...