| d5e2512c | 06-Jan-2022 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex-A510 erratum 2288014
Cortex-A510 erratum 2288014 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
SDEN can be f
fix(errata): workaround for Cortex-A510 erratum 2288014
Cortex-A510 erratum 2288014 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I875519ff55be90244cc3d3a7e9f7abad0fc3c2b8
show more ...
|
| 83435637 | 04-Jan-2022 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex-A510 erratum 1922240
Cortex-A510 erratum 1922240 is a Cat B erratum that applies to revision
r0p0 and is fixed in r0p1.
Since no errata framework code existed for
fix(errata): workaround for Cortex-A510 erratum 1922240
Cortex-A510 erratum 1922240 is a Cat B erratum that applies to revision
r0p0 and is fixed in r0p1.
Since no errata framework code existed for A510 prior to this patch, it
has been added as well. Also some general cleanup changes in the CPU lib
makefile.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I8c427ef255cb4b38ed3e5c2c7444fcef957277e4
show more ...
|
| 8a855bd2 | 06-Feb-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(errata): workaround for Cortex-A710 erratum 2136059
Cortex-A710 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround i
fix(errata): workaround for Cortex-A710 erratum 2136059
Cortex-A710 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR5_EL1[44] to 1 which will cause
the CPP instruction to invalidate the hardware prefetcher state
trained from any EL.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I43a86a365418fb663cc1b6ab1d365b4beddae0bc
show more ...
|
| cfe1a8f7 | 06-Feb-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(errata): workaround for Cortex-A710 erratum 2267065
Cortex-A710 erratum 2267065 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround
fix(errata): workaround for Cortex-A710 erratum 2267065
Cortex-A710 erratum 2267065 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR_EL1[22] to 1'b1. Setting
CPUACTLR_EL1[22] will cause the CFP instruction to invalidate
all branch predictor resources regardless of context.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia9085aaf9b2b6a2b25d03ab36bd3774839fac9aa
show more ...
|
| 4dff7594 | 06-Feb-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(errata): workaround for Cortex-X2 erratum 2216384
Cortex-X2 erratum 2216384 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of CPU. It is fixed in r2p1.
The workaround is to set
fix(errata): workaround for Cortex-X2 erratum 2216384
Cortex-X2 erratum 2216384 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR5_EL1[17] to 1'b1 followed by
applying an instruction patching sequence.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I3c216161678887c06a28c59644e784e0c7d37bab
show more ...
|
| c060b533 | 20-Jan-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(errata): workaround for Cortex-X2 errata 2081180
Cortex-X2 erratum 2081180 is a Cat B erratum present in r0p0, r1p0
and r2p0 of the Cortex-X2 processor core.
Cortex-X2 SDEN: https://developer.a
fix(errata): workaround for Cortex-X2 errata 2081180
Cortex-X2 erratum 2081180 is a Cat B erratum present in r0p0, r1p0
and r2p0 of the Cortex-X2 processor core.
Cortex-X2 SDEN: https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I64bed2fd5b7e12932d6de2ae668786e689885188
show more ...
|
| e16045de | 03-Dec-2021 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex X2 erratum 2058056
Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.
There are
fix(errata): workaround for Cortex X2 erratum 2058056
Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.
There are 2 ways this workaround can be accomplished, the first of
which involves executing a few additional instructions around MSR
writes to CPUECTLR when disabling the prefetcher. (see SDEN for
details)
However, this patch implements the 2nd possible workaround which sets
the prefetcher into its most conservative mode, since this workaround
is generic.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Idb20d9928c986616cd5bedf40bb29d46d384cfd3
show more ...
|
| b36fe212 | 29-Sep-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
errata: workaround for Cortex-A78 erratum 2132060
Cortex-A78 erratum 2132060 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, and r1p2 of CPU. It is still open.
The workaround is to wr
errata: workaround for Cortex-A78 erratum 2132060
Cortex-A78 erratum 2132060 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, and r1p2 of CPU. It is still open.
The workaround is to write the value 2'b11 to the PF_MODE bits
in the CPUECTLR_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: If7dec72578633d37d110d103099e406c3a970ff7
show more ...
|
| 8e140272 | 28-Sep-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
errata: workaround for Neoverse-V1 erratum 2108267
Neoverse-V1 erratum 2108267 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r1p1 of CPU. It is still open. The
workaround is to write
errata: workaround for Neoverse-V1 erratum 2108267
Neoverse-V1 erratum 2108267 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r1p1 of CPU. It is still open. The
workaround is to write the value 2'b11 to the PF_MODE bits in
the CPUECTLR_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: Iedcb84a7ad34af7083116818f49d7296f7d9bf94
show more ...
|