| a055fddd | 27-Oct-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
fix(security): remove CVE_2022_23960 Cortex-X4
Cortex-X4 has ECBHB implemented and is protected against X-Context
attacks.
Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://d
fix(security): remove CVE_2022_23960 Cortex-X4
Cortex-X4 has ECBHB implemented and is protected against X-Context
attacks.
Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://developer.arm.com/documentation/102484/0003/The-Cortex-X4--core/Supported-standards-and-specifications?lang=en
Remove WORKAROUND_CVE_2022_23960 for Cortex-X4 to avoid accidental
enabling of this workaround and using loop workaround.
This was accidentally added with
commit@8c87becbc64f2e233ac905aa006d5e15a63a9a8b
Change-Id: I23f5fa748377a920340b3c5a6584ccfadeea901a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| a2e22acf | 27-Oct-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
fix(security): remove CVE_2022_23960 Neoverse V3
Neoverse V3 has ECBHB implemented and is protected against X-Context
attacks.
Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https
fix(security): remove CVE_2022_23960 Neoverse V3
Neoverse V3 has ECBHB implemented and is protected against X-Context
attacks.
Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://developer.arm.com/documentation/107734/0002/The-Neoverse--V3--core/Supported-standards-and-specifications?lang=en
Remove WORKAROUND_CVE_2022_23960 to avoid accidental enabling of this
workaround and using loop workaround.
This was accidentally added with
commit@c2a15217c3053117f4d39233002cb1830fa96670
Change-Id: I13b27c04c3da5ec80fa79422b4ef4fee64738caa
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| 98ea7329 | 08-Sep-2025 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
fix(cpus): workaround for Neoverse-V2 erratum 3701771
Neoverse-V2 erratum 3701771 that applies to r0p0, r0p1, r0p2 is
still Open.
The workaround is for EL3 software that performs context save/resto
fix(cpus): workaround for Neoverse-V2 erratum 3701771
Neoverse-V2 erratum 3701771 that applies to r0p0, r0p1, r0p2 is
still Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
The mitigation is implemented in commit 7455cd172 and this patch should be applied on top of it.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ic0ad68f7bd393bdc03343d5ba815adb23bf6a24d
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| af1fa796 | 29-Aug-2025 |
John Powell <john.powell@arm.com> |
fix(cpus): workaround for Cortex-A510 erratum 3672349
Cortex-A510 erratum 3672349 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.
fix(cpus): workaround for Cortex-A510 erratum 3672349
Cortex-A510 erratum 3672349 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.
The workaround is to clear the WFE_RET_CTRL and WFI_RET_CTRL fields
in CPUPWRCTLR_EL1 to disable full retention.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/
Change-Id: I9786ab8843a2eab45e650c6af50b6933481527ec
Signed-off-by: John Powell <john.powell@arm.com>
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| 4fb7090e | 29-Aug-2025 |
John Powell <john.powell@arm.com> |
fix(cpus): workaround for Cortex-A510 erratum 2420992
Cortex-A510 erratum 2420992 is a Cat B erratum that applies only to
revisions r1p0 and r1p1, and is fixed in r1p1.
The workaround is to set bit
fix(cpus): workaround for Cortex-A510 erratum 2420992
Cortex-A510 erratum 2420992 is a Cat B erratum that applies only to
revisions r1p0 and r1p1, and is fixed in r1p1.
The workaround is to set bit 3 in CPUACTLR3_EL1 which will have no
performance impact, but will increase power consumption by 0.3-0.5%.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/
Change-Id: Ia76ba2431d76f14c08b95a998806986190d682c3
Signed-off-by: John Powell <john.powell@arm.com>
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