History log of /rk3399_ARM-atf/include/lib/cpus/aarch64/neoverse_n2.h (Results 26 – 32 of 32)
Revision Date Author Comments
# ef03e78f 03-Sep-2021 Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge changes from topic "erratas" into integration

* changes:
errata: workaround for Neoverse N2 erratum 2138956
errata: workaround for Neoverse N2 erratum 2189731
errata: workaround for Cort

Merge changes from topic "erratas" into integration

* changes:
errata: workaround for Neoverse N2 erratum 2138956
errata: workaround for Neoverse N2 erratum 2189731
errata: workaround for Cortex-A710 erratum 2017096
errata: workaround for Cortex-A710 erratum 2055002

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# 7cfae932 30-Aug-2021 Bipin Ravi <bipin.ravi@arm.com>

errata: workaround for Neoverse N2 erratum 2189731

Neoverse N2 erratum 2189731 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR5_EL1[44] to 1 whi

errata: workaround for Neoverse N2 erratum 2189731

Neoverse N2 erratum 2189731 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR5_EL1[44] to 1 which will cause the CPP instruction to
invalidate the hardware prefetcher state trained from any EL.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Iddc6a59adf9fa3cab560c46f2133e1f5a8b3ad03

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# b7942a91 03-Sep-2021 Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge changes from topic "erratas" into integration

* changes:
errata: workaround for Neoverse N2 erratum 2025414
errata: workaround for Neoverse N2 erratum 2067956


# 4618b2bf 31-Mar-2021 Bipin Ravi <bipin.ravi@arm.com>

errata: workaround for Neoverse N2 erratum 2025414

Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which

errata: workaround for Neoverse N2 erratum 2025414

Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia1c63fb93a1bdb1c3f4cf019a197b2a59233885a

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# 65e04f27 30-Mar-2021 Bipin Ravi <bipin.ravi@arm.com>

errata: workaround for Neoverse N2 erratum 2067956

Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force

errata: workaround for Neoverse N2 erratum 2067956

Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r0p0.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ie92d18a379c66675b5c1c50fd0b8dde130848b21

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# 9dd2896e 01-Dec-2020 Lauren Wehrmeister <lauren.wehrmeister@arm.com>

Merge "Add support for Neoverse-N2 CPUs." into integration


# 25bbbd2d 23-Oct-2020 Javier Almansa Sobrino <javier.almansasobrino@arm.com>

Add support for Neoverse-N2 CPUs.

Enable basic support for Neoverse-N2 CPUs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8

Add support for Neoverse-N2 CPUs.

Enable basic support for Neoverse-N2 CPUs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad

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