| #
b667b369 |
| 22-Jun-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "TF-A GIC driver: Add barrier before eoi" into integration
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| #
5eb16c47 |
| 05-Jun-2020 |
Sandeep Tripathy <sandeep.tripathy@broadcom.com> |
TF-A GIC driver: Add barrier before eoi
It is desired to have the peripheral writes completed to clear the interrupt condition and de-assert the interrupt request to GIC before EOI write. Failing wh
TF-A GIC driver: Add barrier before eoi
It is desired to have the peripheral writes completed to clear the interrupt condition and de-assert the interrupt request to GIC before EOI write. Failing which spurious interrupt will occurred.
A barrier is needed to ensure peripheral register write transfers are complete before EOI is done.
GICv2 memory mapped DEVICE nGnR(n)E writes are ordered from core point of view. However these writes may pass over different interconnects, bridges, buffers leaving some rare chances for the actual write to complete out of order.
GICv3 ICC EOI system register writes have no ordering against nGnR(n)E memory writes as they are over different interfaces.
Hence a dsb can ensure from core no writes are issued before the previous writes are *complete*.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Change-Id: Ie6362009e2f91955be99dca8ece14ade7b4811d6
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| #
10640d24 |
| 09-Jun-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "GICv3: GIC-600: Detect GIC-600 at runtime" into integration
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| #
b4ad365a |
| 25-Mar-2020 |
Andre Przywara <andre.przywara@arm.com> |
GICv3: GIC-600: Detect GIC-600 at runtime
The only difference between GIC-500 and GIC-600 relevant to TF-A is the differing power management sequence. A certain GIC implementation is detectable at r
GICv3: GIC-600: Detect GIC-600 at runtime
The only difference between GIC-500 and GIC-600 relevant to TF-A is the differing power management sequence. A certain GIC implementation is detectable at runtime, for instance by checking the IIDR register. Let's add that test before initiating the GIC-600 specific sequence, so the code can be used on both GIC-600 and GIC-500 chips alike, without deciding on a GIC chip at compile time.
This means that the GIC-500 "driver" is now redundant. To allow minimal platform support, add a switch to disable GIC-600 support.
Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| #
994421a6 |
| 07-Apr-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topics "af/fvp_gicv4", "af/gicv4", "af/gic_extended" into integration
* changes: FVP: Add support for GICv4 extension TF-A: Add GICv4 extension for GIC driver TF-A GICv3 dri
Merge changes from topics "af/fvp_gicv4", "af/gicv4", "af/gic_extended" into integration
* changes: FVP: Add support for GICv4 extension TF-A: Add GICv4 extension for GIC driver TF-A GICv3 driver: Add extended PPI and SPI range
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| #
5875f266 |
| 06-Apr-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A: Add GICv4 extension for GIC driver
This patch adds support for GICv4 extension. New `GIC_ENABLE_V4_EXTN` option passed to gicv3.mk makefile was added, and enables GICv4 related changes when se
TF-A: Add GICv4 extension for GIC driver
This patch adds support for GICv4 extension. New `GIC_ENABLE_V4_EXTN` option passed to gicv3.mk makefile was added, and enables GICv4 related changes when set to 1. This option defaults to 0.
Change-Id: I30ebe1b7a98d3a54863900f37eda4589c707a288 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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| #
8f3ad766 |
| 06-Apr-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A GICv3 driver: Add extended PPI and SPI range
This patch provides support for GICv3.1 extended PPI and SPI range. The option is enabled by setting to 1 and passing `GIC_EXT_INTID` build flag to
TF-A GICv3 driver: Add extended PPI and SPI range
This patch provides support for GICv3.1 extended PPI and SPI range. The option is enabled by setting to 1 and passing `GIC_EXT_INTID` build flag to gicv3.mk makefile. This option defaults to 0 with no extended range support.
Change-Id: I7d09086fe22ea531c5df51a8a1efd8928458d394 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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6654d17e |
| 11-Mar-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "TF-A GICv3 driver: Separate GICD and GICR accessor functions" into integration
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| #
6e19bd56 |
| 21-Feb-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A GICv3 driver: Separate GICD and GICR accessor functions
This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3
TF-A GICv3 driver: Separate GICD and GICR accessor functions
This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously.
Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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| #
41bda863 |
| 27-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "mp/giv3-discovery" into integration
* changes: Migrate ARM platforms to use the new GICv3 API Adding new optional PSCI hook pwr_domain_on_finish_late GICv3: Enable mu
Merge changes from topic "mp/giv3-discovery" into integration
* changes: Migrate ARM platforms to use the new GICv3 API Adding new optional PSCI hook pwr_domain_on_finish_late GICv3: Enable multi socket GIC redistributor frame discovery
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| #
ec834925 |
| 15-May-2019 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
GICv3: Enable multi socket GIC redistributor frame discovery
This patch provides declaration and definition of new GICv3 driver API: gicv3_rdistif_probe().This function delegates the responsibility
GICv3: Enable multi socket GIC redistributor frame discovery
This patch provides declaration and definition of new GICv3 driver API: gicv3_rdistif_probe().This function delegates the responsibility of discovering the corresponding Redistributor base frame to each CPU itself. It is a modified version of gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform unlike the previous approach in which only the Primary CPU did the discovery of all the Redistributor frames for every CPU.
The flush operations as part of gicv3_driver_init() function are made necessary even for platforms with WARMBOOT_ENABLE_DCACHE_EARLY because the GICv3 driver data structure contents are accessed by CPU with D-Cache turned off during power down operations.
Change-Id: I1833e81d3974b32a3e4a3df4766a33d070982268 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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01c44ddd |
| 02-Aug-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__" into integration
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| #
d5dfdeb6 |
| 09-Jul-2019 |
Julius Werner <jwerner@chromium.org> |
Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.
All common C compilers predefine a macro called __ASSEMBLER__ when pre
Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.
All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard.
Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
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| #
6eee5864 |
| 25-Jan-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1777 from glneo/runtime-gicr
ti: k3: common: Add support for runtime detection of GICR base address
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| #
b5443284 |
| 22-Jan-2019 |
Andrew F. Davis <afd@ti.com> |
ti: k3: common: Add support for runtime detection of GICR base address
Valid addresses for GICR base are always a set calculable distance from the GICD and is based on the number of cores a given in
ti: k3: common: Add support for runtime detection of GICR base address
Valid addresses for GICR base are always a set calculable distance from the GICD and is based on the number of cores a given instance of GICv3 IP can support. The formula for the number of address bits is given by the ARM GIC-500 TRM section 3.2 as 2^(18+log2(cores)) with the MSB set to one for GICR instances. Holes in the GIC address space are also guaranteed to safely return 0 on reads. This allows us to support runtime detection of the GICR base address by starting from GIC base address plus BIT(18) and walking until the GICR ID register (IIDR) is detected. We stop searching after BIT(20) to prevent searching out into space if something goes wrong. This can be extended out if we ever have a device with 16 or more cores.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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9a207532 |
| 04-Jan-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1726 from antonio-nino-diaz-arm/an/includes
Sanitise includes across codebase
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| #
09d40e0e |
| 14-Dec-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Sanitise includes across codebase
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH} - inclu
Sanitise includes across codebase
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them).
For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems.
Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| #
9d068f66 |
| 08-Nov-2018 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1673 from antonio-nino-diaz-arm/an/headers
Standardise header guards across codebase
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| #
c3cf06f1 |
| 08-Nov-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Standardise header guards across codebase
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards.
The style that this proje
Standardise header guards across codebase
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards.
The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H.
The exceptions are files that are imported from other projects:
- CryptoCell driver - dt-bindings folders - zlib headers
Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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3ccfcd6e |
| 02-Oct-2018 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1587 from antonio-nino-diaz-arm/an/deprecated
Remove deprecated interfaces for all platforms
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| #
f9ed3cb6 |
| 24-Sep-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
gic: Remove deprecated driver and interfaces
Change-Id: I567a406edb090ae9d109382f6874846a79dd7473 Co-authored-by: Roberto Vargas <roberto.vargas@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ni
gic: Remove deprecated driver and interfaces
Change-Id: I567a406edb090ae9d109382f6874846a79dd7473 Co-authored-by: Roberto Vargas <roberto.vargas@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| #
612fa950 |
| 30-Aug-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1539 from antonio-nino-diaz-arm/an/gic-misra
MISRA fixes for the GIC driver
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| #
3fea9c8b |
| 21-Aug-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
gic: Fix types
Change-Id: I6a2adef87c20f9279446a54b7e69618fba3d2a25 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| #
8782922c |
| 24-Aug-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
gic: Fix definitions
Change-Id: I945029ca26ea2e63f0d92c5f33019b882f23bd72 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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b9f68dfb |
| 13-Aug-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
gic v3: Turn macros into static inline functions
Change-Id: Ib587f12f36810fc7d4f4b8f575195554299b8ed4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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