| #
dcb40592 |
| 05-Nov-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(fdts stm32mp1): correct copyright dates" into integration
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| #
8d260291 |
| 02-Nov-2021 |
Yann Gautier <yann.gautier@st.com> |
fix(fdts stm32mp1): correct copyright dates
Add 2021 year in the file header Copyright line.
Change-Id: I09f7bef1f746c429ff308286169354e58648a1cd
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| #
fea7f369 |
| 29-Oct-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "st_dt_update" into integration
* changes:
fix(fdts stm32mp1): update PLL nodes for ED1/EV1 boards
fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards
feat(fdts st
Merge changes from topic "st_dt_update" into integration
* changes:
fix(fdts stm32mp1): update PLL nodes for ED1/EV1 boards
fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards
feat(fdts stm32mp1): delete nodes for non-used boot devices
fix(fdts stm32mp1): use 'kHz' as kilohertz abbreviation
refactor(fdts stm32mp1): move STM32MP DDR node
feat(fdts stm32mp1): align DT with latest kernel
show more ...
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| #
3e881a88 |
| 17-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards
Set Ethernet source clock on PLL4P. This is required to enable PTP.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ia64fbb
fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards
Set Ethernet source clock on PLL4P. This is required to enable PTP.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ia64fbb681d3f04f2b90f373c5eb044f5daa2836c
show more ...
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| #
e8a953a9 |
| 20-Oct-2021 |
Yann Gautier <yann.gautier@st.com> |
feat(fdts stm32mp1): align DT with latest kernel
Update STM32MP1 device tree files with kernel 5.15.
Change-Id: Id405a79e18c61e80cd2292a4f87b7b9641df9c82
Signed-off-by: Yann Gautier <yann.gautier@s
feat(fdts stm32mp1): align DT with latest kernel
Update STM32MP1 device tree files with kernel 5.15.
Change-Id: Id405a79e18c61e80cd2292a4f87b7b9641df9c82
Signed-off-by: Yann Gautier <yann.gautier@st.com>
show more ...
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| #
dc57bea0 |
| 02-Oct-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fdts: stm32mp1: realign device tree with kernel" into integration
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| #
277d6af5 |
| 18-Sep-2020 |
Yann Gautier <yann.gautier@st.com> |
fdts: stm32mp1: realign device tree with kernel
There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU a
fdts: stm32mp1: realign device tree with kernel
There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU and DSI, but not needed for TF-A
The STM32MP15xC include a cryptography peripheral, add it in a dedicated
file.
There are 4 packages available, for which the IOs number change. Have one
file for each package. The 2 packages AB and AD are added.
STM32157A-DK1 and STM32MP157C-DK2 share most of their features, a common
dkx file is then created.
Some reordering is done in other files, and realign with kernel DT files.
The DDR files are generated with our internal tool, no changes in the
registers values.
Change-Id: I9f2ef00306310abe34b94c2f10fc7a77a10493d1
Signed-off-by: Yann Gautier <yann.gautier@st.com>
show more ...
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