fix(st-clock): correct types in error messages

Replace wrong %d with the correct types.
This issue was found with the compilation flag:
-Wformat-signedness

Change-Id: Iec3817a245f964ce444b59561b777

fix(st-clock): correct types in error messages

Replace wrong %d with the correct types.
This issue was found with the compilation flag:
-Wformat-signedness

Change-Id: Iec3817a245f964ce444b59561b777ce06c51a60a
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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refactor(st-clock): directly use oscillator name

Instead of transmitting an 'enum stm32mp_osc_id', just send
directly the clock name with a 'const char *'

Change-Id: I866b05cbb1685a9b9f80e63dcd5ba7

refactor(st-clock): directly use oscillator name

Instead of transmitting an 'enum stm32mp_osc_id', just send
directly the clock name with a 'const char *'

Change-Id: I866b05cbb1685a9b9f80e63dcd5ba7b1d35fc932
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>

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feat(st-clock): check HSE configuration in serial boot

In case of programmer mode, the bootrom manages to auto-detect
HSE clock configuration. In order to detect a bad device tree
setting in BL2, it

feat(st-clock): check HSE configuration in serial boot

In case of programmer mode, the bootrom manages to auto-detect
HSE clock configuration. In order to detect a bad device tree
setting in BL2, it will crash during programming if the configuration
is not aligned with the auto-detection.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I230697695745d6282d14b1ebfa6e4c4caa0cd8e2

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refactor(st-clock): improve DT parsing for PLL nodes

Add a function to get PLL settings from DT:
"cfg" property is mandatory, an error is generated if not found.
"frac" is optional, default value is

refactor(st-clock): improve DT parsing for PLL nodes

Add a function to get PLL settings from DT:
"cfg" property is mandatory, an error is generated if not found.
"frac" is optional, default value is returned if not found.
"csg" is optional too, a boolean value indicates if it has been
found, and its value is updated.

Store each PLL node validity information, this avoids parsing DT
several times.

Change-Id: I039466fbe1e67d160f7112814e7bb63b661804d0
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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Merge changes from topic "clock_framework" into integration

* changes:
feat(st): use newly introduced clock framework
feat(clk): add a minimal clock framework

feat(st): use newly introduced clock framework

Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /
stm32mp_clk_get_rate() with clk_enable() / clk_disable() /
clk_get_rate().

Change-Id:

feat(st): use newly introduced clock framework

Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /
stm32mp_clk_get_rate() with clk_enable() / clk_disable() /
clk_get_rate().

Change-Id: I15d2ce57b9499211fa522a1b53eeee9cf584c111
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>

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Merge "feat(stm32mp1): preserve the PLL4 settings for USB boot" into integration

feat(stm32mp1): preserve the PLL4 settings for USB boot

The PLL4 can be used by ROM code as the source clock of USB PHYC and,
in this case, the PLL4 configuration must be preserved
with pll4_preserv

feat(stm32mp1): preserve the PLL4 settings for USB boot

The PLL4 can be used by ROM code as the source clock of USB PHYC and,
in this case, the PLL4 configuration must be preserved
with pll4_preserve to avoid USB disturbance.

This patch also adds an error when the clock tree PLL4 configuration
is not the PLL4 configuration used by ROM code; this error allows to
detect a invalid clock tree.

This commit corrects the coverity issue 343023.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I4bae9312a2db8dd342a38e649513d689b13976bb

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Merge changes from topic "st_fixes" into integration

* changes:
fix(stpmic1): fix power switches activation
fix(stpmic1): update error cases return
refactor(stpmic1): use BIT and GENMASK helpe

Merge changes from topic "st_fixes" into integration

* changes:
fix(stpmic1): fix power switches activation
fix(stpmic1): update error cases return
refactor(stpmic1): use BIT and GENMASK helpers
fix(stm32mp1_clk): keep RTC clock always on
fix(stm32mp1_clk): set other clocks as always on

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Merge "fix(stm32mp1_clk): fix MPU clock rate" into integration

Merge "fix(stm32mp1_clk): fix MCU/AXI parent clock" into integration

fix(stm32mp1_clk): keep RTC clock always on

On battery powered systems the RTC keeps the date/time across
system reboot.
The RTC clock should not be disabled otherwise the date/time
counter gets sto

fix(stm32mp1_clk): keep RTC clock always on

On battery powered systems the RTC keeps the date/time across
system reboot.
The RTC clock should not be disabled otherwise the date/time
counter gets stopped.

Tag RTC clock as always on.

Signed-off-by: HE Shushan <shushan.he@st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Change-Id: I6455c3c740d2e5add28255eb84f8ebaf2870d9d8

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fix(stm32mp1_clk): fix MPU clock rate

MPUDIV dividers are stored in a constant array, under bit shifts form.
They must be used in this way by the clock driver.

Change-Id: If758f7a4048eff956067a10a4

fix(stm32mp1_clk): fix MPU clock rate

MPUDIV dividers are stored in a constant array, under bit shifts form.
They must be used in this way by the clock driver.

Change-Id: If758f7a4048eff956067a10a42ab0983a20a000d
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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fix(stm32mp1_clk): fix MCU/AXI parent clock

Correct MCU clock parent selector: MCU subsystem clock is derived
from clock PLL3_P, not PLL3.

Correct AXI clock parent selector: AXI subsystem clock is

fix(stm32mp1_clk): fix MCU/AXI parent clock

Correct MCU clock parent selector: MCU subsystem clock is derived
from clock PLL3_P, not PLL3.

Correct AXI clock parent selector: AXI subsystem clock is derived
from clock PLL2_P, not PLL2.

This change also renames MCU clock and AXI clock resources to
prevent confusion.

Change-Id: If55618d180e7dce8e4f0977b0e586a6fa8ef28d1
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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fix(stm32mp1_clk): set other clocks as always on

AXI, MPU and MCU clocks are always on, put them in the list
in the function clock_is_always_on().

Change-Id: I969a442274d2da6c59636f3293de1c31b4c8e3

fix(stm32mp1_clk): set other clocks as always on

AXI, MPU and MCU clocks are always on, put them in the list
in the function clock_is_always_on().

Change-Id: I969a442274d2da6c59636f3293de1c31b4c8e3b1
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge changes from topic "st_fixes" into integration

* changes:
fix(stm32_console): do not skip init for crash console
fix(plat/st): add UART reset in crash console init
refactor(stm32mp1_clk)

Merge changes from topic "st_fixes" into integration

* changes:
fix(stm32_console): do not skip init for crash console
fix(plat/st): add UART reset in crash console init
refactor(stm32mp1_clk): update RCC registers file
fix(stm32mp1_clk): keep RTCAPB clock always on
fix(stm32mp1_clk): fix RTC clock rating
fix(stm32mp1_clk): correctly manage RTC clock source
fix(spi_nand): check correct manufacturer id
fix(spi_nand): check that parameters have been set

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refactor(stm32mp1_clk): update RCC registers file

The file is first generated with the peripheral spirit XML file.
And then we add some common definition, to ease driver development.

Change-Id: I4c

refactor(stm32mp1_clk): update RCC registers file

The file is first generated with the peripheral spirit XML file.
And then we add some common definition, to ease driver development.

Change-Id: I4c222cf006caf27cda6da044eaf184ce66bb1442
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(stm32mp1_clk): keep RTCAPB clock always on

Further information such as boot instance are sent over backup
registers. In order to guarantee direct access to backup registers
in uboot, we will kee

fix(stm32mp1_clk): keep RTCAPB clock always on

Further information such as boot instance are sent over backup
registers. In order to guarantee direct access to backup registers
in uboot, we will keep the RTC clock enabled.

Change-Id: I16572d422bfebbf39190a87db8046df486ce91c8
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(stm32mp1_clk): fix RTC clock rating

When RTC clock source is HSE, the RTCDIV is not taken into account.

Change-Id: I1613b638e8932c03f3349adb01e13f5294a3bf5d
Signed-off-by: Gabriel Fernandez <ga

fix(stm32mp1_clk): fix RTC clock rating

When RTC clock source is HSE, the RTCDIV is not taken into account.

Change-Id: I1613b638e8932c03f3349adb01e13f5294a3bf5d
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(stm32mp1_clk): correctly manage RTC clock source

The clksrc value contains the RCC register address and the clock
source number. When applying the clock source, we should filter out
the RCC regi

fix(stm32mp1_clk): correctly manage RTC clock source

The clksrc value contains the RCC register address and the clock
source number. When applying the clock source, we should filter out
the RCC register address from the given value.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4345b03de7b9afd1df78df4131431cf1eb43ec17

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Merge changes from topic "st_fixes" into integration

* changes:
fix(plat/st): correct IO compensation disabling
fix(plat/st): correct BSEC error code management
fix(drivers/st/pmic): missing e

Merge changes from topic "st_fixes" into integration

* changes:
fix(plat/st): correct IO compensation disabling
fix(plat/st): correct BSEC error code management
fix(drivers/st/pmic): missing error check
fix(drivers/st/pmic): initialize i2c_state
fix(drivers/st/clk): use correct return value

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fix(drivers/st/clk): use correct return value

The function stm32mp1_clk_init() returns an int. Return a negative
error value if the device tree is not found.

Change-Id: I422d5fea46c4d63d55a5b62e1db

fix(drivers/st/clk): use correct return value

The function stm32mp1_clk_init() returns an int. Return a negative
error value if the device tree is not found.

Change-Id: I422d5fea46c4d63d55a5b62e1db154c1f53f41b7
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge changes from topic "stm32mp1_plat_updates" into integration

* changes:
docs: update STM32MP1 with versions details
stm32mp1: get peripheral base address from a define
stm32mp1: add finis

Merge changes from topic "stm32mp1_plat_updates" into integration

* changes:
docs: update STM32MP1 with versions details
stm32mp1: get peripheral base address from a define
stm32mp1: add finished good variant in board identifier

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stm32mp1: get peripheral base address from a define

Retrieve peripheral base address from a define instead of
parsing the device tree. The goal is to improve execution time.

Signed-off-by: Pascal P

stm32mp1: get peripheral base address from a define

Retrieve peripheral base address from a define instead of
parsing the device tree. The goal is to improve execution time.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I2588c53ad3d4abcc3d7fe156458434a7940dd72b

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Merge changes from topic "stm32_drivers_update" into integration

* changes:
clk: stm32mp1: fix rcc mckprot status
drivers: st: add missing includes in ETZPC header
mmc: st: clear some flags be

Merge changes from topic "stm32_drivers_update" into integration

* changes:
clk: stm32mp1: fix rcc mckprot status
drivers: st: add missing includes in ETZPC header
mmc: st: clear some flags before sending a command
mmc: st: correct retries management
nand: raw_nand: fix timeout issue in nand_wait_ready
mtd: spi_nor: change message level on macronix detection
gpio: stm32_gpio: check GPIO node status after checking DT
crypto: stm32_hash: fix issue when restarting computation

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