| 49593cc1 | 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
fix(plat/rcar): change process that copy code to system ram
Change processing of invalidate instruction cache to after changing
the RAM attribute.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.
fix(plat/rcar): change process that copy code to system ram
Change processing of invalidate instruction cache to after changing
the RAM attribute.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # squash with rcar_gen3: drivers: Disable data cache while Suspend To RAM
Change-Id: I61339fc5415b26074b1e0753da4c4a432e8f83d9
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| c77ab18e | 13-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
fix(plat/rcar): fix cache maintenance process of reading cert header
Move calling inv_dcache_range from before io_read to after that.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
S
fix(plat/rcar): fix cache maintenance process of reading cert header
Move calling inv_dcache_range from before io_read to after that.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ic0dabf3eb94eeeb04099ed5127cdfda79bbac9b3
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| 993d809c | 20-Mar-2021 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
feat(drivers/rcar3): add extra offset if booting B-side
In case MFISBTSTSR bit 4 is 1, that means the loader was started as
B-side. Load the remaining boot components from 8 MiB offset.
Signed-off-
feat(drivers/rcar3): add extra offset if booting B-side
In case MFISBTSTSR bit 4 is 1, that means the loader was started as
B-side. Load the remaining boot components from 8 MiB offset.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I11d882f30ca4f0cf55fd28d3470ff1063d350d10
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| 053c1346 | 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
feat(plat/rcar3): modify SWDT counter setting for R-Car D3
Modified the SWDT counter setting for R-Car D3.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Oga
feat(plat/rcar3): modify SWDT counter setting for R-Car D3
Modified the SWDT counter setting for R-Car D3.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: If1fa12bf644486f3fad3c6b54cda6c4cbb604103
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| 042d710d | 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
feat(plat/rcar3): update DDR setting for R-Car D3
Update R-Car D3 DDR setting rev.0.02.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.o
feat(plat/rcar3): update DDR setting for R-Car D3
Update R-Car D3 DDR setting rev.0.02.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I3e3a202fbb0ff1f0f38a968ab5f8633604a46432
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| 14f0a081 | 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
feat(plat/rcar3): add process of SSCG setting for R-Car D3
- Added the condition where output the SSCG (MD12) setting
to log for R-Car D3.
- Added the process to switching the bit rate of SCIF by
feat(plat/rcar3): add process of SSCG setting for R-Car D3
- Added the condition where output the SSCG (MD12) setting
to log for R-Car D3.
- Added the process to switching the bit rate of SCIF by the
SSCG (MD12) setting value for R-Car D3.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Iaf07fa4df12dc233af0b57569ee4fa9329f670a9
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| d10f8767 | 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR
Modified the operation register to clearing the state bit of
the SYSCISR register from SYSCISR to SYSCISCR.
Signed-off-by: Hidey
feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR
Modified the operation register to clearing the state bit of
the SYSCISR register from SYSCISR to SYSCISCR.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I9a0820b6414425fa2f4197f60852137827414a4d
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| 4379a3e9 | 30-Nov-2020 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB
Add new board revision for 8GB 1rank of Salvator-XS/H3ULCB
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Si
feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB
Add new board revision for 8GB 1rank of Salvator-XS/H3ULCB
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I9e0ef7340d92de9c892fc5bd04abe24ad6ee4286
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| 726050b8 | 08-Dec-2020 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
feat(drivers/rcar3): ddr: add function to judge a DDR rank
This commit adds the function to change the settings used for DDR
initialization depending on the board ID and DDR rank.
Signed-off-by: To
feat(drivers/rcar3): ddr: add function to judge a DDR rank
This commit adds the function to change the settings used for DDR
initialization depending on the board ID and DDR rank.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I94d550cea620748f5b15499fed1b791a69d61592
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| ec767c1b | 30-Oct-2020 |
Chiaki Fujii <chiaki.fujii.wj@renesas.com> |
fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N
[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.41.
Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Yoshifumi H
fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N
[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.41.
Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Idd2fbea621365d84b566748b5b7d7fb2f0d08168
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| b757d3a1 | 30-Nov-2020 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
fix(drivers/rcar3): i2c_dvfs: fix I2C operation
This commit fixes value to write to the ICCR register according to
the hardware manual.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hi
fix(drivers/rcar3): i2c_dvfs: fix I2C operation
This commit fixes value to write to the ICCR register according to
the hardware manual.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I1f612a482c012a6739e2f31db80224b222df766c
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| 2c10d4e2 | 19-Mar-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
drivers: renesas: common: watchdog: Add support for RZ/G2E
Add watchdog support for RZ/G2E SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.da
drivers: renesas: common: watchdog: Add support for RZ/G2E
Add watchdog support for RZ/G2E SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ia813e051f6605028d0bb83967893ebd107fc8551
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| 5bfea97e | 29-Dec-2020 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
drivers: renesas: rzg: Add PFC support for RZ/G2E
Add pin control support for RZ/G2E SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@b
drivers: renesas: rzg: Add PFC support for RZ/G2E
Add pin control support for RZ/G2E SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I736724cc0dd32f2169018ed7f2f48319b039b61f
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| 30663f34 | 19-Mar-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the
same.
Signed-off-by: Lad Prabhakar <prabhakar.ma
drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the
same.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I454fb40af4f8ce6c4c0d2a53edb307326efd02df
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| bf007a56 | 18-Mar-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC
Select MMC_CH1 for eMMC on RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Da
drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC
Select MMC_CH1 for eMMC on RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib584b5203f38423ffe2ab52c6e6922f5b34a33ee
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