feat: adding the diphda platform

This commit enables trusted-firmware-a with Trusted Board Boot support
for the Diphda 64-bit platform.

Diphda uses a FIP image located in the flash. The FIP contain

feat: adding the diphda platform

This commit enables trusted-firmware-a with Trusted Board Boot support
for the Diphda 64-bit platform.

Diphda uses a FIP image located in the flash. The FIP contains the
following components:

- BL2
- BL31
- BL32
- BL32 SPMC manifest
- BL33
- The TBB certificates

The board boot relies on CoT (chain of trust). The trusted-firmware-a
BL2 is extracted from the FIP and verified by the Secure Enclave
processor. BL2 verification relies on the signature area at the
beginning of the BL2 image. This area is needed by the SecureEnclave
bootloader.

Then, the application processor is released from reset and starts by
executing BL2.

BL2 performs the actions described in the trusted-firmware-a TBB design
document.

Signed-off-by: Rui Miguel Silva <rui.silva@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Change-Id: Iddb1cb9c2a0324a9635e23821c210ac81dfc305d

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docs: update supported FVP models as per release 11.15.14

Change-Id: I65da6ead356e3f4ee47c5a6bf391f65309bafcdd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1

For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The un

feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1

For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The underlying changes for enabling PIE in aarch32 is submitted in
commit 4324a14bf

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib8bb860198b3f97cdc91005503a3184d63e15469

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docs: change Linaro release version to 20.01

We currently use Linaro release software stack version
20.01 in the CI. Reflect that change in the docs.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm

docs: change Linaro release version to 20.01

We currently use Linaro release software stack version
20.01 in the CI. Reflect that change in the docs.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I0fa9f0163afb0bf399ec503abe9af4f17231f173

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Merge "feat(tc0): add support for trusted services" into integration

docs(juno): update TF-A build instructions

Clean up instructions for building/running TF-A on the
Juno platform and add correct link to SCP binaries.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm

docs(juno): update TF-A build instructions

Clean up instructions for building/running TF-A on the
Juno platform and add correct link to SCP binaries.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I536f98082e167edbf45f29ca23cc0db44687bb3b

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feat(tc0): add support for trusted services

This patch adds support for the crypto and secure storage secure
partitions for the Total Compute platform. These secure partitions
have to be managed by

feat(tc0): add support for trusted services

This patch adds support for the crypto and secure storage secure
partitions for the Total Compute platform. These secure partitions
have to be managed by Hafnium executing at S-EL2

Change-Id: I2df690e3a99bf6bf50e2710994a905914a07026e
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>

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docs: revert FVP versions for select models

Reverting FVP versions to previous version 11.12.38 for Cortex-A32x4
and Neoverse-N2x4.

Change-Id: I81e8ad24794dd425a9e9a66dc8bb02b42191abf1
Signed-off-b

docs: revert FVP versions for select models

Reverting FVP versions to previous version 11.12.38 for Cortex-A32x4
and Neoverse-N2x4.

Change-Id: I81e8ad24794dd425a9e9a66dc8bb02b42191abf1
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Merge "docs: update list of supported FVP platforms" into integration

docs: update list of supported FVP platforms

Updated the list of supported FVP platforms as per the latest FVP
release.

Change-Id: I1abd0a7885b1133715062ee1b176733556a4820e
Signed-off-by: Lauren We

docs: update list of supported FVP platforms

Updated the list of supported FVP platforms as per the latest FVP
release.

Change-Id: I1abd0a7885b1133715062ee1b176733556a4820e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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docs: add build options for GPT support enablement

Documented the build options used in Arm GPT parser enablement.

Change-Id: I9d7ef2f44b8f9d2731dd17c2639e5ed0eb6d0b3a
Signed-off-by: Manish V Badar

docs: add build options for GPT support enablement

Documented the build options used in Arm GPT parser enablement.

Change-Id: I9d7ef2f44b8f9d2731dd17c2639e5ed0eb6d0b3a
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(plat/sgi): introduce platform variant build option

A Neoverse reference design platform can have two or more variants that
differ in core count, cluster count or other peripherals. To allow reu

feat(plat/sgi): introduce platform variant build option

A Neoverse reference design platform can have two or more variants that
differ in core count, cluster count or other peripherals. To allow reuse
of platform code across all the variants of a platform, introduce build
option CSS_SGI_PLATFORM_VARIANT for Arm Neoverse reference design
platforms. The range of allowed values for the build option is platform
specific. The recommended range is an interval of non negative integers.

An example usage of the build option is
make PLAT=rdn2 CSS_SGI_PLATFORM_VARIANT=1

Change-Id: Iaae79c0b4d0dc700521bf6e9b4979339eafe0359
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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Add SiP service to configure Arm Ethos-N NPU

By default the Arm Ethos-N NPU will boot up in secure mode. In this mode
the non-secure world cannot access the registers needed to use the NPU.
To still

Add SiP service to configure Arm Ethos-N NPU

By default the Arm Ethos-N NPU will boot up in secure mode. In this mode
the non-secure world cannot access the registers needed to use the NPU.
To still allow the non-secure world to use the NPU, a SiP service has
been added that can delegate non-secure access to the registers needed
to use it.

Only the HW_CONFIG for the Arm Juno platform has been updated to include
the device tree for the NPU and the platform currently only loads the
HW_CONFIG in AArch64 builds.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2

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docs: Add GIC600AE FVP model version information

Added GIC600AE FVP model version information.

Change-Id: I15d25fbdb8e09900976d5993032ec049f8db79f2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe

docs: Add GIC600AE FVP model version information

Added GIC600AE FVP model version information.

Change-Id: I15d25fbdb8e09900976d5993032ec049f8db79f2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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doc: Build option to protect GICR frame

Added a build option 'FVP_GICR_REGION_PROTECTION' to make
redistributor frame of fused/unused cores as read only.

Change-Id: Ie85f86e2465b93321a92a888ce8712a

doc: Build option to protect GICR frame

Added a build option 'FVP_GICR_REGION_PROTECTION' to make
redistributor frame of fused/unused cores as read only.

Change-Id: Ie85f86e2465b93321a92a888ce8712a3144e4ccb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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docs: update fvp version to be used for rdv1 platform

Move RD-V1 platform to use version of FVP_RD_Daniel from 11.10 build 36
to 11.13 build 10

Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

docs: update fvp version to be used for rdv1 platform

Move RD-V1 platform to use version of FVP_RD_Daniel from 11.10 build 36
to 11.13 build 10

Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I9622c03d342bb780234dec8ffe4ab11d8069acab

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docs: arm: Add OPTEE_SP_FW_CONFIG

This adds documentation for device tree build flag OPTEE_SP_FW_CONFIG.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ie45f075cf04

docs: arm: Add OPTEE_SP_FW_CONFIG

This adds documentation for device tree build flag OPTEE_SP_FW_CONFIG.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ie45f075cf04182701007f87aa0c8912cd567157a

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doc: Update list of supported FVP platforms

Updated the list of supported FVP platforms with support for RD-N2 FVP.

Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386
Signed-off-by: Aditya Angadi

doc: Update list of supported FVP platforms

Updated the list of supported FVP platforms with support for RD-N2 FVP.

Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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Merge "doc: Update list of supported FVP platforms" into integration

morello: Add Morello platform documentation

Morello platform has a SCP which brings the primary Rainier CPU
out of reset which starts executing at BL31.

This patch provides documentation support fo

morello: Add Morello platform documentation

Morello platform has a SCP which brings the primary Rainier CPU
out of reset which starts executing at BL31.

This patch provides documentation support for Morello platform.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I38f596668e2b14862d543fabc04549ff34bfb8a2

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doc: Update list of supported FVP platforms

Updated the list of supported FVP platform as per latest
FVP platform release.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I45e

doc: Update list of supported FVP platforms

Updated the list of supported FVP platform as per latest
FVP platform release.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I45ef79aff147ed598a3a92ab6f6b277f7f70604a

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arm_fpga: Add platform documentation

As the Arm Ltd. FPGA port is now working for all existing images, add
some documentation file.

Change-Id: I9e2c532ed15bbc121bb54b3dfc1bdfee8f1443a6
Signed-off-b

arm_fpga: Add platform documentation

As the Arm Ltd. FPGA port is now working for all existing images, add
some documentation file.

Change-Id: I9e2c532ed15bbc121bb54b3dfc1bdfee8f1443a6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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plat/arm: Use common build flag for using generic sp804 driver

SP804 TIMER is not platform specific, and current code base adds
multiple defines to use this driver. Like FVP_USE_SP804_TIMER and
FVP_

plat/arm: Use common build flag for using generic sp804 driver

SP804 TIMER is not platform specific, and current code base adds
multiple defines to use this driver. Like FVP_USE_SP804_TIMER and
FVP_VE_USE_SP804_TIMER.

This patch removes platform specific build flag and adds generic
flag `USE_SP804_TIMER` to be set to 1 by platform if needed.

Change-Id: I5ab792c189885fd1b98ddd187f3a38ebdd0baba2
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "SPM: build OP-TEE as an S-EL1 Secure Partition" into integration

Fix broken links to various sections across docs

These broken links were found with the help of this command:
$> sphinx-build -M linkcheck . build

A sample broken link is reported as follows:
(line

Fix broken links to various sections across docs

These broken links were found with the help of this command:
$> sphinx-build -M linkcheck . build

A sample broken link is reported as follows:
(line 80) -local- firmware-design.rst#secure-el1-payloads-and-dispatchers

Change-Id: I5dcefdd4b8040908658115647e957f6c2c5da7c2
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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