Merge "feat(gicv3): enlarge the range for intr_num of structure interrupt_prop_t" into integration

build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section name

build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be
difficult to select in linker scripts when there is a lack of a
delimiter.

This change introduces the period prefix to all specialized section
names.

BREAKING-CHANGE: All input and output linker section names have been
prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.

Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(gicv3): enlarge the range for intr_num of structure interrupt_prop_t

As the max ESPI can be 5119, so enlarge the intr_num range of
structure interrupt_prop_t. After the patch the ESPI can be ad

feat(gicv3): enlarge the range for intr_num of structure interrupt_prop_t

As the max ESPI can be 5119, so enlarge the intr_num range of
structure interrupt_prop_t. After the patch the ESPI can be add to
this macro:
define PLATFORM_G1S_PROPS(grp) \
INTR_PROP_DESC(197 - 32 + 4576, GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(199 - 32 + 4576, GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE)

The firmware-design.rst will be updated accordingly.

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: Ic923868bb1b00c017410dc2aeabfda58ee54782f

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Merge "feat: pass SMCCCv1.3 SVE hint bit to dispatchers" into integration

feat: pass SMCCCv1.3 SVE hint bit to dispatchers

SMCCCv1.3 introduces the SVE hint bit added to the SMC FID (bit 16)
denoting that the world issuing an SMC doesn't expect the callee to
preserve the

feat: pass SMCCCv1.3 SVE hint bit to dispatchers

SMCCCv1.3 introduces the SVE hint bit added to the SMC FID (bit 16)
denoting that the world issuing an SMC doesn't expect the callee to
preserve the SVE state (FFR, predicates, Zn vector bits greater than
127). Update the generic SMC handler to copy the SVE hint bit state
to SMC flags and mask out the bit by default for the services called
by the standard dispatcher. It is permitted by the SMCCC standard to
ignore the bit as long as the SVE state is preserved. In any case a
callee must preserve the NEON state (FPCR/FPSR, Vn 128b vectors)
whichever the SVE hint bit state.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I2b163ed83dc311b8f81f96b23c942829ae9fa1b5

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Merge changes from topic "refactor-hw-config-load" into integration

* changes:
docs(fvp): update loading addresses of HW_CONFIG
docs(fconf): update device tree binding for FCONF
feat(fvp): upd

Merge changes from topic "refactor-hw-config-load" into integration

* changes:
docs(fvp): update loading addresses of HW_CONFIG
docs(fconf): update device tree binding for FCONF
feat(fvp): update HW_CONFIG DT loading mechanism
refactor(st): update set_config_info function call
refactor(fvp_r): update set_config_info function call
refactor(arm): update set_config_info function call
feat(fconf): add NS load address in configuration DTB nodes

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docs(fvp): update loading addresses of HW_CONFIG

As per change [1], now HW_CONFIG gets loaded in secure and
non-secure memory. Hence updated the documentation to show
secure and non-secure load regi

docs(fvp): update loading addresses of HW_CONFIG

As per change [1], now HW_CONFIG gets loaded in secure and
non-secure memory. Hence updated the documentation to show
secure and non-secure load region of HW_CONFIG in FVP Arm
platform.

Additionally, added a note on how FW_CONFIG address gets
passed from BL2 to BL31/SP_MIN.

[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/14620

Change-Id: I37e02ff4f433c87bccbe67c7df5ecde3017668b9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes I9e6feeee,If1cd7962 into integration

* changes:
docs(rme): add description of TF-A changes for RME
docs(gpt): add documentation page for GPT library

docs(rme): add description of TF-A changes for RME

This patch expands the RME documentation with description of TF-A
changes for RME. It also modifies some other parts of TF-A documentation
to accou

docs(rme): add description of TF-A changes for RME

This patch expands the RME documentation with description of TF-A
changes for RME. It also modifies some other parts of TF-A documentation
to account for RME changes.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I9e6feeee235f0ba4b767d239f15840f1e0c540bb

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Merge "fix: remove "experimental" tag for stable features" into integration

fix: remove "experimental" tag for stable features

there are features which are marked as experimental even though they
are stable and used for quite some time.
Following features are no longer mark

fix: remove "experimental" tag for stable features

there are features which are marked as experimental even though they
are stable and used for quite some time.
Following features are no longer marked as experimental
- SPMD
- MEASURED_BOOT
- FCONF and associated build flags
- DECRYPTION_SUPPORT and associated build flags
- ENABLE_PAUTH
- ENABLE_BTI
- USE_SPINLOCK_CAS
- GICv3 Multichip support

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I4bb653d9c413c66095ec31f0b8aefeb13ea04ee9

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Merge "doc: Correct CPACR.FPEN usage" into integration

doc: Correct CPACR.FPEN usage

To avoid trapping from EL0/1, FPEN bits need to be set 0x3, not
clearing.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: Ic34e9aeb876872883c5f040618ed6d50f21dac

doc: Correct CPACR.FPEN usage

To avoid trapping from EL0/1, FPEN bits need to be set 0x3, not
clearing.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: Ic34e9aeb876872883c5f040618ed6d50f21dacd0

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Merge "Fix broken links to various sections across docs" into integration

Fix broken links to various sections across docs

These broken links were found with the help of this command:
$> sphinx-build -M linkcheck . build

A sample broken link is reported as follows:
(line

Fix broken links to various sections across docs

These broken links were found with the help of this command:
$> sphinx-build -M linkcheck . build

A sample broken link is reported as follows:
(line 80) -local- firmware-design.rst#secure-el1-payloads-and-dispatchers

Change-Id: I5dcefdd4b8040908658115647e957f6c2c5da7c2
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "Fix broken link in documentation" into integration

Fix broken link in documentation

The link to the exception handling framework page on the System Design /
Firmware Design / Section 4.3 just links to itself, so I changed it to
link to the exception

Fix broken link in documentation

The link to the exception handling framework page on the System Design /
Firmware Design / Section 4.3 just links to itself, so I changed it to
link to the exception handling framework component document.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I6711b423a789b2b3d1921671e8497fffa8ba33d1

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Merge changes from topic "fw_config_handoff" into integration

* changes:
doc: Update memory layout for firmware configuration area
plat/arm: Increase size of firmware configuration area
plat/a

Merge changes from topic "fw_config_handoff" into integration

* changes:
doc: Update memory layout for firmware configuration area
plat/arm: Increase size of firmware configuration area
plat/arm: Load and populate fw_config and tb_fw_config
fconf: Handle error from fconf_load_config
plat/arm: Update the fw_config load call and populate it's information
fconf: Allow fconf to load additional firmware configuration
fconf: Clean confused naming between TB_FW and FW_CONFIG
tbbr/dualroot: Add fw_config image in chain of trust
cert_tool: Update cert_tool for fw_config image support
fiptool: Add fw_config in FIP
plat/arm: Rentroduce tb_fw_config device tree

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doc: Update memory layout for firmware configuration area

Captured the increase in firmware configuration area from
4KB to 8kB in memory layout document. Updated the documentation
to provide details

doc: Update memory layout for firmware configuration area

Captured the increase in firmware configuration area from
4KB to 8kB in memory layout document. Updated the documentation
to provide details about fw_config separately.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ifbec443ced479301be65827b49ff4fe447e9109f

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Merge "doc: Fixup some SMCCC links" into integration

doc: Fixup some SMCCC links

This is a fixup for patch 3ba55a3c5fa260c9218be1adff8f39fc2a568d68
("docs: Update SMCCC doc, other changes for release"), where some
links names got changed but their ref

doc: Fixup some SMCCC links

This is a fixup for patch 3ba55a3c5fa260c9218be1adff8f39fc2a568d68
("docs: Update SMCCC doc, other changes for release"), where some
links names got changed but their references didn't.

Change-Id: I980d04dde338f3539a2ec1ae2e807440587b1cf5
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge "docs: Update SMCCC doc, other changes for release" into integration

docs: Update SMCCC doc, other changes for release

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ie842d6a9919776de151a4e9304f870aede07c47a

Merge "juno/sgm: Maximize space allocated to SCP_BL2" into integration

juno/sgm: Maximize space allocated to SCP_BL2

To accommodate the increasing size of the SCP_BL2 binary, the base
address of the memory region allocated to SCP_BL2 has been moved
downwards from its c

juno/sgm: Maximize space allocated to SCP_BL2

To accommodate the increasing size of the SCP_BL2 binary, the base
address of the memory region allocated to SCP_BL2 has been moved
downwards from its current (mostly) arbitrary address to the beginning
of the non-shared trusted SRAM.

Change-Id: I086a3765bf3ea88f45525223d765dc0dbad6b434
Signed-off-by: Chris Kay <chris.kay@arm.com>

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