| #
b7942a91 |
| 03-Sep-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "erratas" into integration
* changes:
errata: workaround for Neoverse N2 erratum 2025414
errata: workaround for Neoverse N2 erratum 2067956
|
| #
9dc2534f |
| 02-Sep-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "errata: workaround for Cortex-A78 errata 1952683" into integration
|
| #
4618b2bf |
| 31-Mar-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
errata: workaround for Neoverse N2 erratum 2025414
Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which
errata: workaround for Neoverse N2 erratum 2025414
Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia1c63fb93a1bdb1c3f4cf019a197b2a59233885a
show more ...
|
| #
65e04f27 |
| 30-Mar-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
errata: workaround for Neoverse N2 erratum 2067956
Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force
errata: workaround for Neoverse N2 erratum 2067956
Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r0p0.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ie92d18a379c66675b5c1c50fd0b8dde130848b21
show more ...
|
| #
3c9962a1 |
| 30-Aug-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "errata: workaround for Neoverse-N2 errata 2002655" into integration
|
| #
523569d0 |
| 30-Aug-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I1e8c2bc3,I9bcff306 into integration
* changes:
errata: workaround for Cortex-A710 errata 2081180
errata: workaround for Cortex-A710 errata 1987031
|
| #
9380f754 |
| 07-Aug-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
errata: workaround for Neoverse-N2 errata 2002655
Neoverse-N2 erratum 2002655 is a Cat B erratum present in r0p0 of
the Neoverse-N2 processor core, and it is still open.
Neoverse-N2 SDEN: https://d
errata: workaround for Neoverse-N2 errata 2002655
Neoverse-N2 erratum 2002655 is a Cat B erratum present in r0p0 of
the Neoverse-N2 processor core, and it is still open.
Neoverse-N2 SDEN: https://documentation-service.arm.com/static/61098b4e3d73a34b640e32c9?token=
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I1380418146807527abd97cdd4918265949ba5c01
show more ...
|
| #
d0464435 |
| 26-Aug-2021 |
Varun Wadekar <vwadekar@nvidia.com> |
Merge "feat(cpus): workaround for Cortex A78 AE erratum 1941500" into integration
|
| #
a64bcc2b |
| 26-Aug-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
errata: workaround for Cortex-A710 errata 2081180
Cortex-A710 erratum 2081180 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.
A710 SDEN:
errata: workaround for Cortex-A710 errata 2081180
Cortex-A710 erratum 2081180 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.
A710 SDEN: https://developer.arm.com/documentation/SDEN1775101/1000
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I1e8c2bc3d8dc326947ccfd91daf9083d666b2542
show more ...
|
| #
fbcf54ae |
| 06-Aug-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
errata: workaround for Cortex-A710 errata 1987031
Cortex-A710 erratum 1987031 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.
A710 SDEN:
errata: workaround for Cortex-A710 errata 1987031
Cortex-A710 erratum 1987031 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.
A710 SDEN: https://documentation-service.arm.com/static/61099dc59ebe3a7dbd3a8a88?token=
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I9bcff306f82328ad5a0f6e9836020d23c07f7179
show more ...
|
| #
00bee997 |
| 11-Aug-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
errata: workaround for Cortex-A78 errata 1952683
Cortex-A78 erratum 1952683 is a Cat B erratum present in r0p0 of
the Cortex-A78 processor core, and it was fixed in r1p0.
A78 SDEN : https://develop
errata: workaround for Cortex-A78 errata 1952683
Cortex-A78 erratum 1952683 is a Cat B erratum present in r0p0 of
the Cortex-A78 processor core, and it was fixed in r1p0.
A78 SDEN : https://developer.arm.com/documentation/SDEN1401784/1400
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I77b03e695532cb13e8f8d3f00c43d973781ceeb0
show more ...
|
| #
47d6f5ff |
| 27-Jul-2021 |
Varun Wadekar <vwadekar@nvidia.com> |
feat(cpus): workaround for Cortex A78 AE erratum 1941500
Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.
This erratum is avoided by by setting
feat(cpus): workaround for Cortex A78 AE erratum 1941500
Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.
This erratum is avoided by by setting CPUECTLR_EL1[8] to 1.
There is a small performance cost (<0.5%) for setting this
bit.
SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900
Change-Id: I2d72666468b146714a0340ba114ccf0f5165b39c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| #
0ed87212 |
| 19-Aug-2021 |
Varun Wadekar <vwadekar@nvidia.com> |
Merge "feat(cpus): workaround for Cortex A78 AE erratum 1951502" into integration
|
| #
8913047a |
| 27-Jul-2021 |
Varun Wadekar <vwadekar@nvidia.com> |
feat(cpus): workaround for Cortex A78 AE erratum 1951502
Cortex A78 AE erratum 1951502 is a Cat B erratum that applies to revisions
<= r0p1. It is still open. This erratum is avoided by inserting a
feat(cpus): workaround for Cortex A78 AE erratum 1951502
Cortex A78 AE erratum 1951502 is a Cat B erratum that applies to revisions
<= r0p1. It is still open. This erratum is avoided by inserting a DMB ST
before acquire atomic instructions without release semantics through a series
of writes to implementation defined system registers.
SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900
Change-Id: I812c5a37cdd03486df8af6046d9fa988f6a0a098
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| #
0d6aff20 |
| 10-Aug-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 2139242" into integration
|
| #
9aacfb6f |
| 10-Aug-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 1966096" into integration
|
| #
100d4029 |
| 03-Aug-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Neoverse V1 errata 2139242
Neoverse V1 erratum 2139242 is a Cat B erratum present in the V1
processor core. This issue is present in revisions r0p0, r1p0,
and r1p1, and it is
errata: workaround for Neoverse V1 errata 2139242
Neoverse V1 erratum 2139242 is a Cat B erratum present in the V1
processor core. This issue is present in revisions r0p0, r1p0,
and r1p1, and it is still open.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I5c2e9beec72a64ac4131fb6dd76199821a934ebe
show more ...
|
| #
1a8804c3 |
| 02-Aug-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Neoverse V1 errata 1966096
Neoverse V1 erratum 1966096 is a Cat B erratum present in the V1
processor core. This issue is present in revisions r0p0, r1p0,
and r1p1, but the w
errata: workaround for Neoverse V1 errata 1966096
Neoverse V1 erratum 1966096 is a Cat B erratum present in the V1
processor core. This issue is present in revisions r0p0, r1p0,
and r1p1, but the workaround only applies to r1p0 and r1p1, it is still
open.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic0b9a931e38da8a7000648e221481e17c253563b
show more ...
|
| #
d1987f4c |
| 09-Aug-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 1925756" into integration
|
| #
55120f9c |
| 09-Aug-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 1852267" into integration
|
| #
1d24eb33 |
| 09-Aug-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 1774420" into integration
|
| #
741dd04c |
| 02-Aug-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
errata: workaround for Neoverse V1 errata 1925756
Neoverse V1 erratum 1925756 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the V1 processor core, and it is still open.
SDEN can be found he
errata: workaround for Neoverse V1 errata 1925756
Neoverse V1 erratum 1925756 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the V1 processor core, and it is still open.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I6500dc98da92a7c405b9ae09d794d666e8f4ae52
show more ...
|
| #
143b1965 |
| 02-Aug-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
errata: workaround for Neoverse V1 errata 1852267
Neoverse V1 erratum 1852267 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
http
errata: workaround for Neoverse V1 errata 1852267
Neoverse V1 erratum 1852267 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ide5e0bc09371fbc91c2385ffdff74e604beb2dbe
show more ...
|
| #
4789cf66 |
| 02-Aug-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
errata: workaround for Neoverse V1 errata 1774420
Neoverse V1 erratum 1774420 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
http
errata: workaround for Neoverse V1 errata 1774420
Neoverse V1 erratum 1774420 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I66e27b2518f73faeedd8615a1443a74b6a30f123
show more ...
|
| #
c31c82df |
| 19-Jul-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 1940577" into integration
|