feat(neoverse_rd): deprecate and remove SGI-575 platform

deprecate and remove support for SGI-575 platform.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iffee2fa8f4faa463c4b4df5911

feat(neoverse_rd): deprecate and remove SGI-575 platform

deprecate and remove support for SGI-575 platform.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iffee2fa8f4faa463c4b4df591182f72a461c880b

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Merge "docs(maintainers): update Sumit Garg's email address" into integration

docs(maintainers): update Sumit Garg's email address

Update Sumit Garg's email address to @kernel.org.

Change-Id: I405ce9b0f59643dd7cb05d69ceadd15dcd536eef
Signed-off-by: Sumit Garg <sumit.garg@lin

docs(maintainers): update Sumit Garg's email address

Update Sumit Garg's email address to @kernel.org.

Change-Id: I405ce9b0f59643dd7cb05d69ceadd15dcd536eef
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

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Merge changes I3d950e72,Id315a8fe,Ib62e6e9b,I1d0475b2 into integration

* changes:
perf(cm): drop ZCR_EL3 saving and some ISBs and replace them with root context
perf(psci): get PMF timestamps wi

Merge changes I3d950e72,Id315a8fe,Ib62e6e9b,I1d0475b2 into integration

* changes:
perf(cm): drop ZCR_EL3 saving and some ISBs and replace them with root context
perf(psci): get PMF timestamps with no cache flushes if possible
perf(amu): greatly simplify AMU context management
perf(mpmm): greatly simplify MPMM enablement

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perf(mpmm): greatly simplify MPMM enablement

MPMM is a core-specific microarchitectural feature. It has been present
in every Arm core since the Cortex-A510 and has been implemented in
exactly the s

perf(mpmm): greatly simplify MPMM enablement

MPMM is a core-specific microarchitectural feature. It has been present
in every Arm core since the Cortex-A510 and has been implemented in
exactly the same way. Despite that, it is enabled more like an
architectural feature with a top level enable flag. This utilised the
identical implementation.

This duality has left MPMM in an awkward place, where its enablement
should be generic, like an architectural feature, but since it is not,
it should also be core-specific if it ever changes. One choice to do
this has been through the device tree.

This has worked just fine so far, however, recent implementations expose
a weakness in that this is rather slow - the device tree has to be read,
there's a long call stack of functions with many branches, and system
registers are read. In the hot path of PSCI CPU powerdown, this has a
significant and measurable impact. Besides it being a rather large
amount of code that is difficult to understand.

Since MPMM is a microarchitectural feature, its correct placement is in
the reset function. The essence of the current enablement is to write
CPUPPMCR_EL3.MPMM_EN if CPUPPMCR_EL3.MPMMPINCTL == 0. Replacing the C
enablement with an assembly macro in each CPU's reset function achieves
the same effect with just a single close branch and a grand total of 6
instructions (versus the old 2 branches and 32 instructions).

Having done this, the device tree entry becomes redundant. Should a core
that doesn't support MPMM arise, this can cleanly be handled in the
reset function. As such, the whole ENABLE_MPMM_FCONF and platform hooks
mechanisms become obsolete and are removed.

Change-Id: I1d0475b21a1625bb3519f513ba109284f973ffdf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "docs(maintainers): update LTS maintainers" into integration

docs(maintainers): update LTS maintainers

Updating LTS maintainers list as agreed with other LTS
maintainers.

Change-Id: Ibf087c6b0e24d6faa9dafb6f8a0955a47f583f28
Signed-off-by: Govindraj Raja <gov

docs(maintainers): update LTS maintainers

Updating LTS maintainers list as agreed with other LTS
maintainers.

Change-Id: Ibf087c6b0e24d6faa9dafb6f8a0955a47f583f28
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "gr/lts-doc" into integration

* changes:
docs: updates to LTS
docs: add inital lts doc

docs: add inital lts doc

Ref: https://linaro.atlassian.net/browse/TFC-669

The initial LTS document was created as pdf and was maintained in a
shared folder location, to avoid pdf getting lost and t

docs: add inital lts doc

Ref: https://linaro.atlassian.net/browse/TFC-669

The initial LTS document was created as pdf and was maintained in a
shared folder location, to avoid pdf getting lost and trying to find
where it is we decided to have LTS details part of docs in TF-A.

This patch directly reflects the data from pdf attached to TFC-669.
Any improvements or amends to this will be done at later phases based
on LTS maintainers comments and agreements.

Change-Id: I1434c29f0236161d2a127596e2cc528bf4cc3e85
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "docs(maintainers): update marvell maintainer" into integration

docs(maintainers): update marvell maintainer

Add Jaiprakash Singh as marvell maintainer

Change-Id: Ica924c0502b0a271b0368255841ef413391de959
Signed-off-by: Jaiprakash Singh <jaiprakashs@marvell.com>

Merge "docs(maintainers): update qti maintainer" into integration

Merge "docs: add Govind as new TF-A maintainer" into integration

docs: add Govind as new TF-A maintainer

Also update Raghu's email address.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Icea15fa5eaf5413b0be7c42e8ef376cfeb9d5f27

docs(maintainers): update qti maintainer

Add Saurabh Gorecha in qti maintainer

Change-Id: I24c8453288444ec9f60dca7c4019fd1635090b33
Signed-off-by: Bharath N <quic_bharn@quicinc.com>

Merge changes from topic "rd1ae-upstream" into integration

* changes:
docs(rd1ae): add RD-1 AE documentation
feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE
feat(rd1ae): introduce BL

Merge changes from topic "rd1ae-upstream" into integration

* changes:
docs(rd1ae): add RD-1 AE documentation
feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE
feat(rd1ae): introduce BL31 for RD-1 AE platform
feat(rd1ae): add device tree files
feat(rd1ae): introduce Arm RD-1 AE platform
build(bl2): enable check for bl2 base overflow assert
feat(arm): add support for loading CONFIG from BL2

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feat(rd1ae): introduce Arm RD-1 AE platform

Create a new platform for the RD-1 AE automotive FVP.
This platform contains:
* Neoverse-V3AE, Arm9.2-A application processor
* A GICv4-compatible GIC-7

feat(rd1ae): introduce Arm RD-1 AE platform

Create a new platform for the RD-1 AE automotive FVP.
This platform contains:
* Neoverse-V3AE, Arm9.2-A application processor
* A GICv4-compatible GIC-720AE
* 128 MB of SRAM, of which 1 MB is reserved for TF-A

and BL2 runs at ELmax (EL3).

Additionally, this commit updates the maintainers.rst file and
the changelog.yaml to add scope for RD-1 AE variants.

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Signed-off-by: Divin Raj <divin.raj@arm.com>
Signed-off-by: Rahul Singh <rahul.singh@arm.com>
Change-Id: I9ae64b3f05a52653ebd1d334b15b7f21821264e2

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Merge "docs(maintainers): remove jwerner from Rockchip" into integration

docs(maintainers): remove jwerner from Rockchip

I originally added myself here because I had experience with the rk3399
code, when there were no other maintainers and that was the only
supported Roc

docs(maintainers): remove jwerner from Rockchip

I originally added myself here because I had experience with the rk3399
code, when there were no other maintainers and that was the only
supported Rockchip SoC. Nowadays there are maintainers from the actual
manufacturer and most changes concern other SoCs, so I don't think it
makes sense for me to still be on here.

Change-Id: Id75089e62cf1a8b4cf1a27903808922968520636
Signed-off-by: Julius Werner <jwerner@chromium.org>

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Merge "docs(maintainers): update Corstone-1000 maintainers" into integration

docs(maintainers): update Corstone-1000 maintainers

* Add new maintainers: Hugues Kamba Mpiana
* Remove maintainers: Xueliang Zhong
* Update contact information for existing maintainers

Change-Id:

docs(maintainers): update Corstone-1000 maintainers

* Add new maintainers: Hugues Kamba Mpiana
* Remove maintainers: Xueliang Zhong
* Update contact information for existing maintainers

Change-Id: Ie4b7e7a1a179e3bf6f8d8e6c8e7ff0ad788e9f8f
Signed-off-by: Hugues Kamba-Mpiana <hugues.kambampiana@arm.com>

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Merge changes from topic "add_s32cc_clk_skeleton" into integration

* changes:
feat(s32g274a): use s32cc clock driver
feat(nxp-drivers): add clock skeleton for s32cc

feat(nxp-drivers): add clock skeleton for s32cc

The S32CC is an umbrella for S32G2, S32G3 and S32R45 SoCs; therefore,
this clock driver will be used for all of these families.

Change-Id: Iede5371b2

feat(nxp-drivers): add clock skeleton for s32cc

The S32CC is an umbrella for S32G2, S32G3 and S32R45 SoCs; therefore,
this clock driver will be used for all of these families.

Change-Id: Iede5371b212b67cf494a033c62fbfdcbe9b1a879
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "docs(maintainers): update the maintainer list for LTS" into integration

docs(maintainers): update the maintainer list for LTS

This patch updates the maintainer list for LTS.

Change-Id: I7942288cd79dd163bebd3397bf908bf29906d59e
Signed-off-by: Bipin Ravi <bipin.ravi@arm.

docs(maintainers): update the maintainer list for LTS

This patch updates the maintainer list for LTS.

Change-Id: I7942288cd79dd163bebd3397bf908bf29906d59e
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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