| #
1839012d |
| 13-Jul-2021 |
Zelalem Aweke <zelalem.aweke@arm.com> |
feat(rme): add GPT Library
This patch introduces the Granule Protection Table (GPT) library code. This implementation will be updated later to be more flexible, as the current implementation is very
feat(rme): add GPT Library
This patch introduces the Granule Protection Table (GPT) library code. This implementation will be updated later to be more flexible, as the current implementation is very rigid.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I3af824a28c6e9a5d36459c0c51d2d9bebfba1505
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| #
77c27753 |
| 09-Jul-2021 |
Zelalem Aweke <zelalem.aweke@arm.com> |
feat(rme): add RMM dispatcher (RMMD)
This patch introduces the RMM dispatcher into BL31. This will be the mechanism that will enable communication to take place between the Realm and non-secure worl
feat(rme): add RMM dispatcher (RMMD)
This patch introduces the RMM dispatcher into BL31. This will be the mechanism that will enable communication to take place between the Realm and non-secure world. Currently gives the capability for granules to be transitioned from non-secure type to realm and vice versa.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com> Change-Id: I1fdc99a4bdd42bc14911aa0c6954b131de309511
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| #
b3210f4d |
| 17-Sep-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "TrcDbgExt" into integration
* changes: feat(plat/fvp): enable trace extension features by default feat(trf): enable trace filter control register access from lower NS E
Merge changes from topic "TrcDbgExt" into integration
* changes: feat(plat/fvp): enable trace extension features by default feat(trf): enable trace filter control register access from lower NS EL feat(trf): initialize trap settings of trace filter control registers access feat(sys_reg_trace): enable trace system registers access from lower NS ELs feat(sys_reg_trace): initialize trap settings of trace system registers access feat(trbe): enable access to trace buffer control registers from lower NS EL feat(trbe): initialize trap settings of trace buffer control registers access
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| #
8fcd3d96 |
| 08-Jul-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(trf): enable trace filter control register access from lower NS EL
Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter control registers access in NS-EL2, or NS-EL1 (when NS-EL2
feat(trf): enable trace filter control register access from lower NS EL
Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is implemented but unused).
Change-Id: If3f53b8173a5573424b9a405a4bd8c206ffdeb8c Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| #
d4582d30 |
| 29-Jun-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace system registers access in NS-EL2, or NS-EL1 (when N
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace system registers access in NS-EL2, or NS-EL1 (when NS-EL2 is implemented but unused).
Change-Id: Idc1acede4186e101758cbf7bed5af7b634d7d18d Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| #
813524ea |
| 02-Jul-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(trbe): enable access to trace buffer control registers from lower NS EL
Introduced a build flag 'ENABLE_TRBE_FOR_NS' to enable trace buffer control registers access in NS-EL2, or NS-EL1 (when N
feat(trbe): enable access to trace buffer control registers from lower NS EL
Introduced a build flag 'ENABLE_TRBE_FOR_NS' to enable trace buffer control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is implemented but unused).
Change-Id: I285a672ccd395eebd377714c992bb21062a729cc Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| #
e55d12b7 |
| 27-May-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "Arm_PCI_Config_Space_Interface" into integration
* changes: TF-A: Document SMC_PCI_SUPPORT option SMCCC/PCI: Handle std svc boilerplate SMCCC/PCI: Add initial PCI con
Merge changes from topic "Arm_PCI_Config_Space_Interface" into integration
* changes: TF-A: Document SMC_PCI_SUPPORT option SMCCC/PCI: Handle std svc boilerplate SMCCC/PCI: Add initial PCI conduit definitions SMCCC: Hoist SMC_32 sanitization
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| #
1cdf1eb8 |
| 18-Nov-2020 |
Jeremy Linton <jeremy.linton@arm.com> |
SMCCC/PCI: Handle std svc boilerplate
Add SMC wrappers for handshaking the existence and basic parameter validation for the SMCCC/PCI API. The actual read/write/segment validation is implemented by
SMCCC/PCI: Handle std svc boilerplate
Add SMC wrappers for handshaking the existence and basic parameter validation for the SMCCC/PCI API. The actual read/write/segment validation is implemented by a given platform which will enable the API by defining SMC_PCI_SUPPORT.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Change-Id: I4485ad0fe6003cec6f5eedef688914d100513c21
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| #
6080aac9 |
| 05-Feb-2021 |
André Przywara <andre.przywara@arm.com> |
Merge "Add TRNG Firmware Interface service" into integration
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| #
7dfb9911 |
| 22-Jun-2020 |
Jimmy Brisson <jimmy.brisson@arm.com> |
Add TRNG Firmware Interface service
This adds the TRNG Firmware Interface Service to the standard service dispatcher. This includes a method for dispatching entropy requests to platforms and include
Add TRNG Firmware Interface service
This adds the TRNG Firmware Interface Service to the standard service dispatcher. This includes a method for dispatching entropy requests to platforms and includes an entropy pool implementation to avoid dropping any entropy requested from the platform.
Change-Id: I71cadb3cb377a507652eca9e0d68714c973026e9 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| #
29a8814f |
| 15-Dec-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "Add support for FEAT_MTPMU for Armv8.6" into integration
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| #
0063dd17 |
| 23-Nov-2020 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
Add support for FEAT_MTPMU for Armv8.6
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented as well, it is possible to control whether PMU counters take into account events happ
Add support for FEAT_MTPMU for Armv8.6
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented as well, it is possible to control whether PMU counters take into account events happening on other threads.
If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit leaving it to effective state of 0 regardless of any write to it.
This patch introduces the DISABLE_MTPMU flag, which allows to diable multithread event count from EL3 (or EL2). The flag is disabled by default so the behavior is consistent with those architectures that do not implement FEAT_MTPMU.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
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| #
478fc4f2 |
| 28-Sep-2020 |
André Przywara <andre.przywara@arm.com> |
Merge "arm_fpga: Add support for unknown MPIDs" into integration
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| #
1994e562 |
| 20-Aug-2020 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
arm_fpga: Add support for unknown MPIDs
This patch allows the system to fallback to a default CPU library in case the MPID does not match with any of the supported ones.
This feature can be enabled
arm_fpga: Add support for unknown MPIDs
This patch allows the system to fallback to a default CPU library in case the MPID does not match with any of the supported ones.
This feature can be enabled by setting SUPPORT_UNKNOWN_MPID build option to 1 (enabled by default only on arm_fpga platform).
This feature can be very dangerous on a production image and therefore it MUST be disabled for Release images.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I0df7ef2b012d7d60a4fd5de44dea1fbbb46881ba
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| #
c1a4b6b4 |
| 21-Sep-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "build_macros.mk: include assert and define loop macros" into integration
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| #
327131c4 |
| 10-Sep-2020 |
Leonardo Sandoval <leonardo.sandoval@linaro.org> |
build_macros.mk: include assert and define loop macros
Loop macros make it easier for developers to include new variables to assert or define and also help code code readability on makefiles.
Chang
build_macros.mk: include assert and define loop macros
Loop macros make it easier for developers to include new variables to assert or define and also help code code readability on makefiles.
Change-Id: I0d21d6e67b3eca8976c4d856ac8ccc02c8bb5ffa Signed-off-by: Leonardo Sandoval <leonardo.sandoval@linaro.org>
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| #
63aa4094 |
| 11-Feb-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "spmd" into integration
* changes: SPMD: enable SPM dispatcher support SPMD: hook SPMD into standard services framework SPMD: add SPM dispatcher based upon SPCI Beta 0
Merge changes from topic "spmd" into integration
* changes: SPMD: enable SPM dispatcher support SPMD: hook SPMD into standard services framework SPMD: add SPM dispatcher based upon SPCI Beta 0 spec SPMD: add support to run BL32 in TDRAM and BL31 in secure DRAM on Arm FVP SPMD: add support for an example SPM core manifest SPMD: add SPCI Beta 0 specification header file
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| #
c3fb00d9 |
| 11-Oct-2019 |
Achin Gupta <achin.gupta@arm.com> |
SPMD: enable SPM dispatcher support
This patch adds support to the build system to include support for the SPM dispatcher when the SPD configuration option is spmd.
Signed-off-by: Achin Gupta <achi
SPMD: enable SPM dispatcher support
This patch adds support to the build system to include support for the SPM dispatcher when the SPD configuration option is spmd.
Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Change-Id: Ic1ae50ecd7403fcbcf1d318abdbd6ebdc642f732
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| #
be84a5b9 |
| 20-Dec-2019 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "debugfs: add 9p device interface" into integration
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| #
91ecca23 |
| 20-Dec-2019 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "spm-devel" into integration
* changes: spm-mm: Rename aarch64 assembly files spm-mm: Rename source files spm-mm: Rename spm_shim_private.h spm-mm: Rename spm_privat
Merge changes from topic "spm-devel" into integration
* changes: spm-mm: Rename aarch64 assembly files spm-mm: Rename source files spm-mm: Rename spm_shim_private.h spm-mm: Rename spm_private.h spm-mm: Rename component makefile spm-mm: Remove mm_svc.h header spm-mm: Refactor spm_svc.h and its contents spm-mm: Refactor secure_partition.h and its contents spm: Remove SPM Alpha 1 prototype and support files Remove dependency between SPM_MM and ENABLE_SPM build flags
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| #
442e0928 |
| 15-Oct-2019 |
Paul Beesley <paul.beesley@arm.com> |
spm-mm: Rename component makefile
Change-Id: Idcd2a35cd2b30d77a7ca031f7e0172814bdb8cab Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| #
538b0020 |
| 14-Oct-2019 |
Paul Beesley <paul.beesley@arm.com> |
spm: Remove SPM Alpha 1 prototype and support files
The Secure Partition Manager (SPM) prototype implementation is being removed. This is preparatory work for putting in place a dispatcher component
spm: Remove SPM Alpha 1 prototype and support files
The Secure Partition Manager (SPM) prototype implementation is being removed. This is preparatory work for putting in place a dispatcher component that, in turn, enables partition managers at S-EL2 / S-EL1.
This patch removes:
- The core service files (std_svc/spm) - The Resource Descriptor headers (include/services) - SPRT protocol support and service definitions - SPCI protocol support and service definitions
Change-Id: Iaade6f6422eaf9a71187b1e2a4dffd7fb8766426 Signed-off-by: Paul Beesley <paul.beesley@arm.com> Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
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| #
3f3c341a |
| 16-Sep-2019 |
Paul Beesley <paul.beesley@arm.com> |
Remove dependency between SPM_MM and ENABLE_SPM build flags
There are two different implementations of Secure Partition management in TF-A. One is based on the "Management Mode" (MM) design, the oth
Remove dependency between SPM_MM and ENABLE_SPM build flags
There are two different implementations of Secure Partition management in TF-A. One is based on the "Management Mode" (MM) design, the other is based on the Secure Partition Client Interface (SPCI) specification. Currently there is a dependency between their build flags that shouldn't exist, making further development harder than it should be. This patch removes that dependency, making the two flags function independently.
Before: ENABLE_SPM=1 is required for using either implementation. By default, the SPCI-based implementation is enabled and this is overridden if SPM_MM=1.
After: ENABLE_SPM=1 enables the SPCI-based implementation. SPM_MM=1 enables the MM-based implementation. The two build flags are mutually exclusive.
Note that the name of the ENABLE_SPM flag remains a bit ambiguous - this will be improved in a subsequent patch. For this patch the intention was to leave the name as-is so that it is easier to track the changes that were made.
Change-Id: I8e64ee545d811c7000f27e8dc8ebb977d670608a Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| #
0ca3913d |
| 19-Sep-2019 |
Olivier Deprez <olivier.deprez@arm.com> |
debugfs: add 9p device interface
The 9p interface provides abstraction layers allowing the software that uses devices to be independent from the hardware.
This patch provides a file system abstract
debugfs: add 9p device interface
The 9p interface provides abstraction layers allowing the software that uses devices to be independent from the hardware.
This patch provides a file system abstraction to link drivers to their devices and propose a common interface to expose driver operations to higher layers. This file system can be used to access and configure a device by doing read/write operations.
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Ia9662393baf489855dc0c8f389fe4a0afbc9c255
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| #
508a48bb |
| 24-May-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "Add support for Branch Target Identification" into integration
|