Add ALIGNMENT_IS_OK to libutils/ext/include/util.h, delete unused code

TEE_ALIGNMENT_IS_OK() is renamed ALIGNMENT_IS_OK() and moved to
lib/libutils/ext/include/util.h, which avoids duplication (was

Add ALIGNMENT_IS_OK to libutils/ext/include/util.h, delete unused code

TEE_ALIGNMENT_IS_OK() is renamed ALIGNMENT_IS_OK() and moved to
lib/libutils/ext/include/util.h, which avoids duplication (was
previously in core/include/kernel/tee_common_unpg.h and
lib/libutee/include/utee_defines.h). Call sites are adjusted
accordingly.

It is assumed that the compiler keyword __alignof__ is available, so
CFG_TC_NO_ALIGNOF is of no use. We also remove unused definitions:
TEE_ALIGNMENT_*B_IS_OK().

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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core: vexpress-juno: enable v8 crypto acceleration

Enables all supported ARMv8 crypto acceleration for the Juno platform.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens W

core: vexpress-juno: enable v8 crypto acceleration

Enables all supported ARMv8 crypto acceleration for the Juno platform.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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arm64: isb after write to cpacr_el1

Add an isb after each write to cpacr_el1 to make sure the register
update has taken effect before next instruction.

Signed-off-by: Jens Wiklander <jens.wiklander

arm64: isb after write to cpacr_el1

Add an isb after each write to cpacr_el1 to make sure the register
update has taken effect before next instruction.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)

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Ensure sctl programming before resuming system

The entry code programms the sctl register to enable
alignment check and disable I/D cache. Need to put an instruction
barrier to ensure sctl programmi

Ensure sctl programming before resuming system

The entry code programms the sctl register to enable
alignment check and disable I/D cache. Need to put an instruction
barrier to ensure sctl programming has taken place before
resuming the system.

Signed-off-by: Ashutosh Singh <ashutosh.singh@arm.com>
Tested-by: Ashutosh Singh <ashutosh.singh@arm.com>
Reviewed-by: James King <james.king@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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arm: mutex: Add file and line to debuginfo

Adds file and line in the sleep and wake log line if CFG_MUTEX_DEBUG=y.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklande

arm: mutex: Add file and line to debuginfo

Adds file and line in the sleep and wake log line if CFG_MUTEX_DEBUG=y.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU,FVP)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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core: arm: remove big lock

Removes big lock leaving TEE Core open to concurrent execution depending
on internal locks around all critical sections.

Signed-off-by: Jens Wiklander <jens.wiklander@lin

core: arm: remove big lock

Removes big lock leaving TEE Core open to concurrent execution depending
on internal locks around all critical sections.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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libutils: make malloc thread-safe

Makes malloc family of functions thread-safe by using an internal mutex
when compiled to be used in TEE Core.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.

libutils: make malloc thread-safe

Makes malloc family of functions thread-safe by using an internal mutex
when compiled to be used in TEE Core.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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core: arm: thread-safe sessions

Make session handling thread-safe with tee_ta_get_session(),
tee_ta_put_session() and tee_ta_unlink_session().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.o

core: arm: thread-safe sessions

Make session handling thread-safe with tee_ta_get_session(),
tee_ta_put_session() and tee_ta_unlink_session().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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core: ltc: enable thread-safety

Enables thread-safety by replacing empty macros for mutex handling with
a real implementation.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by:

core: ltc: enable thread-safety

Enables thread-safety by replacing empty macros for mutex handling with
a real implementation.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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core: ltc: add lock for memory pool

Adds a recursive lock for the memory pool, allowing only one thread at a
time to use the memory pool. This makes a predictable or consistent
worst case for memory

core: ltc: add lock for memory pool

Adds a recursive lock for the memory pool, allowing only one thread at a
time to use the memory pool. This makes a predictable or consistent
worst case for memory pool utilization. It also allows for a controlled
way of releasing memory from the pool to the pager when the pool is
unused.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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core: TEE_GetSystemTime() updates

- Set gpd.tee.systemTime.protectionLevel to 1000 when the time source
is the physical count register (CNTPCT), that is, when
CFG_SECURE_TIME_SOURCE_CNTPCT=y. The pr

core: TEE_GetSystemTime() updates

- Set gpd.tee.systemTime.protectionLevel to 1000 when the time source
is the physical count register (CNTPCT), that is, when
CFG_SECURE_TIME_SOURCE_CNTPCT=y. The protection level value is moved
into the time_source struct for better modularity.
- When the time source is REE (CFG_SECURE_TIME_SOURCE_REE=y), make sure
that successive calls return increasing values as required by the GP
TEE Core Internal API v1.1.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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docs: Allwinner clarifications about availability

The A80 boards exist in both locked (publicly available) an unlocked
versions (to Allwinner partners). Our main documentation has been
updated clari

docs: Allwinner clarifications about availability

The A80 boards exist in both locked (publicly available) an unlocked
versions (to Allwinner partners). Our main documentation has been
updated clarifying that this is the case.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Sunny <sunny@allwinnertech.com>

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docs: Adding column for platform availability

Since not all platforms and devices are readily available we have added
a third column in the matrix stating supported platforms in OP-TEE.

Signed-off-

docs: Adding column for platform availability

Since not all platforms and devices are readily available we have added
a third column in the matrix stating supported platforms in OP-TEE.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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docs: Adding a maintainer file

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

Fix Travis build

The Travis build was broken by optee_test commit 0e00914b378d ("Make
cross compile variables configurable via the environment"), because the
CC environment variable is set to the ho

Fix Travis build

The Travis build was broken by optee_test commit 0e00914b378d ("Make
cross compile variables configurable via the environment"), because the
CC environment variable is set to the host compiler during Travis
builds. Simply unset this variable in the before_script step to avoid
any side-effect.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: bugfix reading char from uart

If debug prints aren't enabled plat-vexpress doesn't read characters
from the uart resulting in an endless loop.

This patch always reads the character r

plat-vexpress: bugfix reading char from uart

If debug prints aren't enabled plat-vexpress doesn't read characters
from the uart resulting in an endless loop.

This patch always reads the character regardless of debug prints.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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DHEXDUMP(): prefix each line with the current address in the buffer

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by:

DHEXDUMP(): prefix each line with the current address in the buffer

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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Docs: import interrupt handling document

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

drivers/core/gic.c: Set priority mask to allow NS interrupts

The non-secure world's view of interrupt priorities only allows
it to set priorities between 0x80 and 0xff. This means that the
secure wo

drivers/core/gic.c: Set priority mask to allow NS interrupts

The non-secure world's view of interrupt priorities only allows
it to set priorities between 0x80 and 0xff. This means that the
secure world has to set the GICC_PMR (priority mask register) to
a value that allows NS interrupts, otherwise the non-secure
world will never see interrupts and has no way to set the
priorities so that it will ever see them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers/core/gic.c: Fix indentation in gic_cpu_init()

The indentation in gic_cpu_init() is using spaces rather than
tabs. Since it's a very short function and we're about to add
some code to it, fix

drivers/core/gic.c: Fix indentation in gic_cpu_init()

The indentation in gic_cpu_init() is using spaces rather than
tabs. Since it's a very short function and we're about to add
some code to it, fix the indentation first.

Fix a comment typo while we're here.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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pager: bug fix boot time moving of hashes

Fixes problem with moving hashes of paged pages during boot. Before MMU is
initialize we invalidate all memory used by TEE Core. In the pager case we
had __

pager: bug fix boot time moving of hashes

Fixes problem with moving hashes of paged pages during boot. Before MMU is
initialize we invalidate all memory used by TEE Core. In the pager case we
had __init_end as end marker but that's not good now that we store the
hashes temporarily at that address. The new end is now __tmp_hashes_end.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: enable paging with concurrent execution

* Updates the pager to handle concurrent execution.
* The pager now supports no execute and readonly pages too.

All physical pages used for paging is a

core: enable paging with concurrent execution

* Updates the pager to handle concurrent execution.
* The pager now supports no execute and readonly pages too.

All physical pages used for paging is also mapped in an aliased area
which is used when preparing a physical page to be mapped at another
virtual address.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP)
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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core: support concurrent use of VFP

Supports concurrent use of VFP by moving the VFP state into struct
thread_ctx. As a consequence VFP can only be used when a thread is
assigned to the CPU. This me

core: support concurrent use of VFP

Supports concurrent use of VFP by moving the VFP state into struct
thread_ctx. As a consequence VFP can only be used when a thread is
assigned to the CPU. This means that the pager can only verify pages
when a thread is active.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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core: wait_queue: sync obj address in debug print

Include address of sync object in wait queue debug prints to easier
locate a contended sync object.

Signed-off-by: Jens Wiklander <jens.wiklander@l

core: wait_queue: sync obj address in debug print

Include address of sync object in wait queue debug prints to easier
locate a contended sync object.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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core: arm: fix initcall alignment in link script

Increases initcall alignment to 8 to work on arm64.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@

core: arm: fix initcall alignment in link script

Increases initcall alignment to 8 to work on arm64.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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