pager: replace mm element of struct tee_pager_area

Replaces the mm element of struct tee_pager_area with base and size
instead to avoid needing a matching mm for every area.

Reviewed-by: Pascal Bra

pager: replace mm element of struct tee_pager_area

Replaces the mm element of struct tee_pager_area with base and size
instead to avoid needing a matching mm for every area.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, Juno)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: rename TEE_MATTR_PHYS_BLOCK

Renames TEE_MATTR_PHYS_BLOCK to TEE_MATTR_HIDDEN_DIRTY_BLOCK.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@lin

core: rename TEE_MATTR_PHYS_BLOCK

Renames TEE_MATTR_PHYS_BLOCK to TEE_MATTR_HIDDEN_DIRTY_BLOCK.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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pager: don't use TEE_MATTR_PHYS_BLOCK

Don't use TEE_MATTR_PHYS_BLOCK to keep track of physical address of a
struct tee_pager_pmem page, read it from the aliased mapping which
always is available and

pager: don't use TEE_MATTR_PHYS_BLOCK

Don't use TEE_MATTR_PHYS_BLOCK to keep track of physical address of a
struct tee_pager_pmem page, read it from the aliased mapping which
always is available and doesn't change.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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pager: optimize alias table lookup

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

Make sure trace_printf() terminates the string with one unique \n

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Jens

Make sure trace_printf() terminates the string with one unique \n

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Update trace format to be less verbose in INFO and ERROR levels

- By default, traces of severity TRACE_INFO or lower will not print
the thread ID, function name or line number. Can be controlled by

Update trace format to be less verbose in INFO and ERROR levels

- By default, traces of severity TRACE_INFO or lower will not print
the thread ID, function name or line number. Can be controlled by
CFG_MSG_LONG_PREFIX_THRESHOLD (see mk/config.mk).
- The trace level string is updated ("DEBUG", "INFO" etc. instead of
"DBG", "INF" etc.) for consistency with ARM Trusted Firmware.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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libutils: add atomic_inc32() and atomic_dec32()

Adds atomic increment and decrement for uint32_t implemented without
privileged instructions.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tes

libutils: add atomic_inc32() and atomic_dec32()

Adds atomic increment and decrement for uint32_t implemented without
privileged instructions.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP, Juno)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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travis: add combinations for 4k page TA mapping

Adds combinations to cover all cases for 4k page TA mapping and without
small page TA mapping.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Si

travis: add combinations for 4k page TA mapping

Adds combinations to cover all cases for 4k page TA mapping and without
small page TA mapping.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: support mapping user TAs with 4k pages

Maps user TAs with small pages (aka 4k pages) if
CFG_SMALL_PAGE_USER_TA = y
If pager is active the translation tables are allocated using
tee_pager_reque

core: support mapping user TAs with 4k pages

Maps user TAs with small pages (aka 4k pages) if
CFG_SMALL_PAGE_USER_TA = y
If pager is active the translation tables are allocated using
tee_pager_request_zi() to only use the physical page when needed.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm: refactor core_mmu*

Refactors core_mmu* to let LPAE and V7 compat table code share some
code for mapping a TA.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander

arm: refactor core_mmu*

Refactors core_mmu* to let LPAE and V7 compat table code share some
code for mapping a TA.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm: fix traces when booting

On plat-stm, traces IP is initialized by Non Secure world.
Hence no traces can be output while in the booting process.

Reviewed-by: Jens Wiklander <jens.wiklander@

plat-stm: fix traces when booting

On plat-stm, traces IP is initialized by Non Secure world.
Hence no traces can be output while in the booting process.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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plat-stm: remove unused code

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

travis: add compile for CFG_TEE_CORE_DEBUG=y

Adds a test compile for CFG_TEE_CORE_DEBUG=y and CFG_WITH_PAGER=y.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <je

travis: add compile for CFG_TEE_CORE_DEBUG=y

Adds a test compile for CFG_TEE_CORE_DEBUG=y and CFG_WITH_PAGER=y.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix build error with CFG_TEE_CORE_DEBUG=y

Fixes build error when CFG_TEE_CORE_DEBUG=y and CFG_WITH_PAGER=y are set
by adding ing CORE_MMU_PGDIR_SIZE and CORE_MMU_PGDIR_MASK.

Reviewed-by: Pasc

core: fix build error with CFG_TEE_CORE_DEBUG=y

Fixes build error when CFG_TEE_CORE_DEBUG=y and CFG_WITH_PAGER=y are set
by adding ing CORE_MMU_PGDIR_SIZE and CORE_MMU_PGDIR_MASK.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Fix potential memory corruptions in elf_load.c when loading TAs

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Suggested-by: Jaso

Fix potential memory corruptions in elf_load.c when loading TAs

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Suggested-by: Jason Lin <Jason.Lin@microsoft.com>
Suggested-by: Paul Swan <Paul.Swan@microsoft.com>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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docs: Remove modprobe instruction

Since we no longer use a dynamically loadable module as the TEE driver
we have removed that from the README.md file.

Signed-off-by: Joakim Bech <joakim.bech@linaro

docs: Remove modprobe instruction

Since we no longer use a dynamically loadable module as the TEE driver
we have removed that from the README.md file.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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plat-ls: tested with Release 2.0.0

Signed-off-by: Pascal Brand <pascal.brand@st.com>

Release Notes 2.0.0

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

Fix wrong comment syntax

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

ARM Juno GP testsuite support note

Signed-off-by: Cedric Chaumont <cedric.chaumont@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

Update Juno documentation

Updates Juno documentation and removes obsolete scripts and patches.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Cedric Chaumont <cedric.chaumont@lina

Update Juno documentation

Updates Juno documentation and removes obsolete scripts and patches.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Cedric Chaumont <cedric.chaumont@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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juno: bug fix initialize TCR_EL1

Prior to this patch TCR_EL1 was incorrectly initialized with bit 32 set
to 0. On Cortex-A57 this bit is RES1 so this bit should always be set to
1, this patch fixes

juno: bug fix initialize TCR_EL1

Prior to this patch TCR_EL1 was incorrectly initialized with bit 32 set
to 0. On Cortex-A57 this bit is RES1 so this bit should always be set to
1, this patch fixes that.

This is related to errata 822227
"Using unsupported 16K translation granules might cause Cortex-A57 to
incorrectly trigger a domain fault"

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Validate the TA signed header's img_size

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Suggested-by: Jason Lin <Jason.Lin@microsoft.com>
Suggested-by: Paul Swan <Paul.Swan@microsoft.com>
S

Validate the TA signed header's img_size

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Suggested-by: Jason Lin <Jason.Lin@microsoft.com>
Suggested-by: Paul Swan <Paul.Swan@microsoft.com>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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stm,vexpress: increase shared memory size from 1 to 2 MiB

This is needed to run the latest "generic driver" configuration.
When the shared memory pool is 1 MiB, xtest 7633 fails with a TA panic
due

stm,vexpress: increase shared memory size from 1 to 2 MiB

This is needed to run the latest "generic driver" configuration.
When the shared memory pool is 1 MiB, xtest 7633 fails with a TA panic
due to memory allocation error. This commit increases the size of the
shared memory pool so that the test will pass.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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core: arm: pager: lock shared accesses

Uses the pager spin-lock for all shared accesses to pager resources.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jerome Forissier <jerome.f

core: arm: pager: lock shared accesses

Uses the pager spin-lock for all shared accesses to pager resources.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...