docs: HiKey on Debian instructions added

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

core: bugfix static TA buffer from user TA

Before this patch the checks of the parameters buffers for a TA where
required to be physical pointers. When a static TA is invoked from a
user TA the virt

core: bugfix static TA buffer from user TA

Before this patch the checks of the parameters buffers for a TA where
required to be physical pointers. When a static TA is invoked from a
user TA the virtual addresses of the buffers aren't translated to
physical addresses as they will be translated back to the same virtual
address again. With this patch the parameters buffers are tagged as
containing virtual addresses allowing the checks to take that into
account.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: bugfix syscall_invoke_ta_command()

Before this patch didn't syscall_invoke_ta_command() update out
parameters if the return code from tee_ta_invoke_command() wasn't
TEE_SUCCESS. With this patc

core: bugfix syscall_invoke_ta_command()

Before this patch didn't syscall_invoke_ta_command() update out
parameters if the return code from tee_ta_invoke_command() wasn't
TEE_SUCCESS. With this patch are out parameters always updated if
tee_ta_invoke_command() has been called.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: map TA with strict permissions

Maps user TA with strict permissions. Blocks with mixed permissions are
mapped with the union of the permissions. In order to take full
advantage of the strict p

core: map TA with strict permissions

Maps user TA with strict permissions. Blocks with mixed permissions are
mapped with the union of the permissions. In order to take full
advantage of the strict permissions TAs should be mapped using small
pages, that is, using the config option CFG_SMALL_PAGE_USER_TA = y.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, Juno)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: imx: fix console address usage

The phyiscal base address of uart console is 0x2020000.
This address conflicts with KMAP address space, so remap it
to 0x4020000.

Signed-off-by: Peng Fan <

core: arm: imx: fix console address usage

The phyiscal base address of uart console is 0x2020000.
This address conflicts with KMAP address space, so remap it
to 0x4020000.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: add cpu_mmu_enabled

Add cpu_mmu_enabled to check mmu enabled or not.
Before mmu, we may use physical address. And after
mmu enabled, we need to use virtual address.

Signed-off-by: Peng F

core: arm: add cpu_mmu_enabled

Add cpu_mmu_enabled to check mmu enabled or not.
Before mmu, we may use physical address. And after
mmu enabled, we need to use virtual address.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: set region_size of map_area dynamically

This patch is to set value to region_size of map_area.

In generic_core_bootcfg.c, there is one place that setting region_size
with CFG_WITH_PAGER

core: arm: set region_size of map_area dynamically

This patch is to set value to region_size of map_area.

In generic_core_bootcfg.c, there is one place that setting region_size
with CFG_WITH_PAGER defined. This means the region_size entry will be
initialized to 0 or 4K with CFG_WITH_PAGER. Also there is no other places
that will write the region_size entry.
However map_pa2va will use map_area->region_size to
calculate the virtual/physical address. So we need to set region_size of
map_area.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: mm: introduce initial value for va

To some SoCs, we can not directly assign physical address
to virtual address. If use LPAE, it is ok to use "va = pa", but
to V7 mmu with LPAE disabled,

core: arm: mm: introduce initial value for va

To some SoCs, we can not directly assign physical address
to virtual address. If use LPAE, it is ok to use "va = pa", but
to V7 mmu with LPAE disabled, va may conflict with user ta and optee
os kernel space address(<= 64M).

1. Introuce a few macros DEVICEx_VA_ADDRESS.
2. Since we have used defined va, we can not directly panic() with
mm->va initialized. If va is not page or section aligned, then panic,
otherwise, all is ok.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: mm: v7: use mm->va to locate the entry of ttb

Use mm->va to locate the entry of ttb, we should not use
mm->pa, because va may be not the same with pa.

Signed-off-by: Peng Fan <van.freeni

core: arm: mm: v7: use mm->va to locate the entry of ttb

Use mm->va to locate the entry of ttb, we should not use
mm->pa, because va may be not the same with pa.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arch: arm correct mme.va initialization

mme.va should be initialized using map[n].va, but not map[n].pa.

Now map[n].pa can make all work, because we use 1 to 1 mapping with
virtual address sa

core: arch: arm correct mme.va initialization

mme.va should be initialized using map[n].va, but not map[n].pa.

Now map[n].pa can make all work, because we use 1 to 1 mapping with
virtual address same to physical address.

Later, we need to implement that virtual address not equal to physical
address to avoid address conflicting with user ta address and optee os
kernel address(<= 64M).

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm: mm: v7: panic when va conficts with KMAP address space

If mm->va is smaller that 64M and bigger that 32M, mm->va
conflicts with KMAP address space

Some SoCs have devices at low addresses, so w

arm: mm: v7: panic when va conficts with KMAP address space

If mm->va is smaller that 64M and bigger that 32M, mm->va
conflicts with KMAP address space

Some SoCs have devices at low addresses, so we need to map at
least those devices at a virtual address which isn't the same
as the physical.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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RPMB: tee_rpmb_write_blk(): allocate buffers once

Allocate shared memory buffers once for the write loop instead of
repeatedly allocating and freeing them. The previous code was needed
due to a bug/

RPMB: tee_rpmb_write_blk(): allocate buffers once

Allocate shared memory buffers once for the write loop instead of
repeatedly allocating and freeing them. The previous code was needed
due to a bug/limitation in optee_linudriver [1]. Now that we are using
the "generic driver", the code can be optimized.

[1] https://github.com/OP-TEE/optee_linuxdriver/issues/40

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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pager: replace mm element of struct tee_pager_area

Replaces the mm element of struct tee_pager_area with base and size
instead to avoid needing a matching mm for every area.

Reviewed-by: Pascal Bra

pager: replace mm element of struct tee_pager_area

Replaces the mm element of struct tee_pager_area with base and size
instead to avoid needing a matching mm for every area.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, Juno)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: rename TEE_MATTR_PHYS_BLOCK

Renames TEE_MATTR_PHYS_BLOCK to TEE_MATTR_HIDDEN_DIRTY_BLOCK.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@lin

core: rename TEE_MATTR_PHYS_BLOCK

Renames TEE_MATTR_PHYS_BLOCK to TEE_MATTR_HIDDEN_DIRTY_BLOCK.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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pager: don't use TEE_MATTR_PHYS_BLOCK

Don't use TEE_MATTR_PHYS_BLOCK to keep track of physical address of a
struct tee_pager_pmem page, read it from the aliased mapping which
always is available and

pager: don't use TEE_MATTR_PHYS_BLOCK

Don't use TEE_MATTR_PHYS_BLOCK to keep track of physical address of a
struct tee_pager_pmem page, read it from the aliased mapping which
always is available and doesn't change.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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pager: optimize alias table lookup

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

Make sure trace_printf() terminates the string with one unique \n

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Jens

Make sure trace_printf() terminates the string with one unique \n

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Update trace format to be less verbose in INFO and ERROR levels

- By default, traces of severity TRACE_INFO or lower will not print
the thread ID, function name or line number. Can be controlled by

Update trace format to be less verbose in INFO and ERROR levels

- By default, traces of severity TRACE_INFO or lower will not print
the thread ID, function name or line number. Can be controlled by
CFG_MSG_LONG_PREFIX_THRESHOLD (see mk/config.mk).
- The trace level string is updated ("DEBUG", "INFO" etc. instead of
"DBG", "INF" etc.) for consistency with ARM Trusted Firmware.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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libutils: add atomic_inc32() and atomic_dec32()

Adds atomic increment and decrement for uint32_t implemented without
privileged instructions.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tes

libutils: add atomic_inc32() and atomic_dec32()

Adds atomic increment and decrement for uint32_t implemented without
privileged instructions.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP, Juno)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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travis: add combinations for 4k page TA mapping

Adds combinations to cover all cases for 4k page TA mapping and without
small page TA mapping.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Si

travis: add combinations for 4k page TA mapping

Adds combinations to cover all cases for 4k page TA mapping and without
small page TA mapping.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: support mapping user TAs with 4k pages

Maps user TAs with small pages (aka 4k pages) if
CFG_SMALL_PAGE_USER_TA = y
If pager is active the translation tables are allocated using
tee_pager_reque

core: support mapping user TAs with 4k pages

Maps user TAs with small pages (aka 4k pages) if
CFG_SMALL_PAGE_USER_TA = y
If pager is active the translation tables are allocated using
tee_pager_request_zi() to only use the physical page when needed.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm: refactor core_mmu*

Refactors core_mmu* to let LPAE and V7 compat table code share some
code for mapping a TA.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander

arm: refactor core_mmu*

Refactors core_mmu* to let LPAE and V7 compat table code share some
code for mapping a TA.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm: fix traces when booting

On plat-stm, traces IP is initialized by Non Secure world.
Hence no traces can be output while in the booting process.

Reviewed-by: Jens Wiklander <jens.wiklander@

plat-stm: fix traces when booting

On plat-stm, traces IP is initialized by Non Secure world.
Hence no traces can be output while in the booting process.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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plat-stm: remove unused code

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

travis: add compile for CFG_TEE_CORE_DEBUG=y

Adds a test compile for CFG_TEE_CORE_DEBUG=y and CFG_WITH_PAGER=y.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <je

travis: add compile for CFG_TEE_CORE_DEBUG=y

Adds a test compile for CFG_TEE_CORE_DEBUG=y and CFG_WITH_PAGER=y.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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