core: add unwind stack in panic

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>

travis: prevent warning from code checking tool

The checkpatch.pl script uses a file called const_structs.checkpatch to
check for correct usage of some kernel structures. We don't want those
checks,

travis: prevent warning from code checking tool

The checkpatch.pl script uses a file called const_structs.checkpatch to
check for correct usage of some kernel structures. We don't want those
checks, which are linux-specific, but we still need the file to be
present otherwise the tool will log a warning message [1].

[1] https://travis-ci.org/OP-TEE/optee_os/builds/167271505#L1720

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

arm32: unwind: print_stack(): fix unwind_state

print_stack() must save r7 and r11 in the unwind_state structure. Not
doing so will likely result in a crash dunring unwind.
Register r7 is typically u

arm32: unwind: print_stack(): fix unwind_state

print_stack() must save r7 and r11 in the unwind_state structure. Not
doing so will likely result in a crash dunring unwind.
Register r7 is typically used as a frame pointer by GCC in Thumb2 mode,
while r11 (a.k.a. fp) is the frame pointer in ARM mode.

Also, set PC to the beginning of print_stack() since there's no point
in going further inside the function.

Fixes: https://github.com/OP-TEE/optee_os/issues/1069
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU)
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

arm32: unwind: mark tee_svc_do_call() with .cantunwind

The assembly function tee_svc_do_call() manipulates the stack pointer
but does not use the proper unwind directives when doing so. As a
result,

arm32: unwind: mark tee_svc_do_call() with .cantunwind

The assembly function tee_svc_do_call() manipulates the stack pointer
but does not use the proper unwind directives when doing so. As a
result, the compiler can't generate proper unwind information. This can
lead to crashes or infinite loops if unwinding is performed at runtime.
Given that there is nothing of much interest below this function, we
simply add a .cantundwind directive to stop unwinding here.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

arm32: unwind: convert int to bool

The return status of unwind_tab() is used as a boolean, so change its
type.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Car

arm32: unwind: convert int to bool

The return status of unwind_tab() is used as a boolean, so change its
type.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

arm32: unwind: fix incorrect return status

After the unwind code was imported from FreeBSD sources, it was slightly
modified to invert some logic. One return slipped through.

Signed-off-by: Jerome

arm32: unwind: fix incorrect return status

After the unwind code was imported from FreeBSD sources, it was slightly
modified to invert some logic. One return slipped through.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: fix spinlock for ARMv7-A and AArch32

Failure to acquire exclusivity when storing locked value on a
spinlock should not yield to wait for an event, just attempting
'strex' execution again.

Tes

core: fix spinlock for ARMv7-A and AArch32

Failure to acquire exclusivity when storing locked value on a
spinlock should not yield to wait for an event, just attempting
'strex' execution again.

Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260/qemu)
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: arm: pad tee-pager.bin to the actual end of data section

Signed-off-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: fix TA memory reference parameters mapping

This change fixes the TA buffer parameter mapping that gets clobbered
when a parameter of lower index relates to nonsecure memory while
a parameter o

core: fix TA memory reference parameters mapping

This change fixes the TA buffer parameter mapping that gets clobbered
when a parameter of lower index relates to nonsecure memory while
a parameter of higher index relates to a secure memory area.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

mm: fix the user L1 mmu entries calculation

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.co

mm: fix the user L1 mmu entries calculation

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>

show more ...

mtk: map entire MEM_AREA_NSEC_SHM area

Running MTK8173 panics in tee_entry_std just after mapping the
arguments. The reason for this is because only 1MB out of 2MB has been
mapped and therefore leav

mtk: map entire MEM_AREA_NSEC_SHM area

Running MTK8173 panics in tee_entry_std just after mapping the
arguments. The reason for this is because only 1MB out of 2MB has been
mapped and therefore leaving a gap between MEM_AREA_NSEC_SHM and
MEM_AREA_TA_RAM. I.e.,

DEBUG: [0x0] TEE-CORE:init_mem_map:398: type va 4
0xbc000000..0xbc0fffff pa 0xbdf00000..0xbdffffff size 0x100000

DEBUG: [0x0] TEE-CORE:init_mem_map:398: type va 3
0xbc200000..0xbdffffff pa 0xbe200000..0xbfffffff size 0x1e00000

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

Update CHANGELOG.md for 2.2.0

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org

Update CHANGELOG.md for 2.2.0

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (d02)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (hikey)
Tested-by: Yan Yan <yan.yan@windriver.com> (imx-mx6qsabrelite)
Tested-by: Yan Yan <yan.yan@windriver.com> (imx-mx6qsabresd)
Tested-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> (rcar-h3)
Tested-by: Joakim Bech <joakim.bech@linaro.org> (rpi3)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm-b2260)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm-cannes)
Tested-by: Harinarayan Bhatta <harinarayan@ti.com> (ti-dra7xx)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (vexpress-fvp)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (vexpress-juno)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (vexpress-qemu_armv8a)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_virt)
Tested-by: Joakim Bech <joakim.bech@linaro.org> (vexpress-qemu_virt)
Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> (zynqmp-zcu102)

show more ...

plat-stm: introduce b2260 (96boards/cannes)

Flavored 'b2260'.
Default no GDB boot, lock pl310, specific DDR size and UART instance.

Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2120/

plat-stm: introduce b2260 (96boards/cannes)

Flavored 'b2260'.
Default no GDB boot, lock pl310, specific DDR size and UART instance.

Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2120/b2260)
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

plat-stm: fix platform

fix PL310 iomem mapped unsecure.
fix rng against nonflat mapping.

Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm-b2120)
Signed-off-by: Etienne Carriere <etien

plat-stm: fix platform

fix PL310 iomem mapped unsecure.
fix rng against nonflat mapping.

Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm-b2120)
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

doc: Update repo xml matrix

- Add qemu_v8_stable.xml, hikey_debian_stable.xml.
- Remove "experimental" part for HiKey running Debian, since we are now
pointing to the official RPB Linux kernel bra

doc: Update repo xml matrix

- Add qemu_v8_stable.xml, hikey_debian_stable.xml.
- Remove "experimental" part for HiKey running Debian, since we are now
pointing to the official RPB Linux kernel branch.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

rpi3: refer to new xml-files in documentation

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

Add maintainers for D02 and Raspberry Pi3

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@

Add maintainers for D02 and Raspberry Pi3

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

crypto: fix incorrect algo passed to cipher.final()

Fix an error in function tee_svc_cipher_update_helper, and add assert
in function cipher_final to prevent it being called by an algorithm
that is

crypto: fix incorrect algo passed to cipher.final()

Fix an error in function tee_svc_cipher_update_helper, and add assert
in function cipher_final to prevent it being called by an algorithm
that is not a symmetric cipher.

Signed-off-by: lackan <liang.guanchao@linaro.org>
[Reword commit subject]
Signed-off-by: Jerome Forissier <jerome.forissier@.linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: add support for paging of user TAs

Enables support for paging of user TAs if CFG_PAGED_USER_TA is y

Acked-by: David Brown <david.brown@linaro.org>
Tested-by: Jerome Forissier <jerome.forissie

core: add support for paging of user TAs

Enables support for paging of user TAs if CFG_PAGED_USER_TA is y

Acked-by: David Brown <david.brown@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU 7)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: arm: kern.ld.S: consistent 8 bytes alignment

Replace the last 4 bytes alignment statements with 8 bytes alignment to
avoid implicit padding when linking the binary.

Implicit padding following

core: arm: kern.ld.S: consistent 8 bytes alignment

Replace the last 4 bytes alignment statements with 8 bytes alignment to
avoid implicit padding when linking the binary.

Implicit padding following the .data section doesn't work with the
pager.

Acked-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

hikey: 32-bit: use -mcpu=cortex-a53 instead of cortex-a15

Use the proper CPU architecture when building 32-bit binaries for HiKey.
Note: this triggers a compiler warning:
CC out/arm-plat-hik

hikey: 32-bit: use -mcpu=cortex-a53 instead of cortex-a15

Use the proper CPU architecture when building 32-bit binaries for HiKey.
Note: this triggers a compiler warning:
CC out/arm-plat-hikey/core/tee/tee_svc_cryp.o
{standard input}: Assembler messages:
{standard input}:632: Warning: IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8
(compiler is gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux).
This seems to be harmless and is registered as a compiler bug [1].

[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67591

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: Add default CFG_CORE_HEAP_SIZE

Adds a CFG_CORE_HEAP_SIZE replacing the defined HEAP_SIZE in each
platform_config.h. Default value is defined in mk/config.mk as 64 kB.
This is larger than most

core: Add default CFG_CORE_HEAP_SIZE

Adds a CFG_CORE_HEAP_SIZE replacing the defined HEAP_SIZE in each
platform_config.h. Default value is defined in mk/config.mk as 64 kB.
This is larger than most of the previous values at 24 kB or just above.

Platforms with a previous heap size defined larger than 64 kB overrides
the mk/config.mk setting with a $(platform-dir)/conf.mk setting using the
previous value.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Hikey pager)
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU v7 pager)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP Aarch32 pager)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: add default CFG_CORE_TZSRAM_EMUL_SIZE

Adds a CFG_CORE_TZSRAM_EMUL_SIZE replacing the previous value directly
defined in TZSRAM_SIZE in each platform_config.h. Default value is
defined in core/

core: add default CFG_CORE_TZSRAM_EMUL_SIZE

Adds a CFG_CORE_TZSRAM_EMUL_SIZE replacing the previous value directly
defined in TZSRAM_SIZE in each platform_config.h. Default value is
defined in core/arch/arm/arm.mk as 300 kB. This is larger than most of
the previous values.

Platforms with TZSRAM_SIZE defined larger than 200 kB overrides the
core/arch/arm/arm.mk setting with a $(platform-dir)/conf.mk setting
using the previous value.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

scripts: Add tee_bin_parser.py

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

scripts: gen_hashed_bin.py Python 3.x support

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>