| 45b45259 | 11-Oct-2016 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: fix TA memory reference parameters mapping
This change fixes the TA buffer parameter mapping that gets clobbered when a parameter of lower index relates to nonsecure memory while a parameter o
core: fix TA memory reference parameters mapping
This change fixes the TA buffer parameter mapping that gets clobbered when a parameter of lower index relates to nonsecure memory while a parameter of higher index relates to a secure memory area.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 095a2999 | 10-Oct-2016 |
Zeng Tao <prime.zeng@hisilicon.com> |
mm: fix the user L1 mmu entries calculation
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Signed-off-by: Zeng Tao <prime.zeng@hisilicon.co
mm: fix the user L1 mmu entries calculation
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
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| 497acca0 | 07-Oct-2016 |
Joakim Bech <joakim.bech@linaro.org> |
mtk: map entire MEM_AREA_NSEC_SHM area
Running MTK8173 panics in tee_entry_std just after mapping the arguments. The reason for this is because only 1MB out of 2MB has been mapped and therefore leav
mtk: map entire MEM_AREA_NSEC_SHM area
Running MTK8173 panics in tee_entry_std just after mapping the arguments. The reason for this is because only 1MB out of 2MB has been mapped and therefore leaving a gap between MEM_AREA_NSEC_SHM and MEM_AREA_TA_RAM. I.e.,
DEBUG: [0x0] TEE-CORE:init_mem_map:398: type va 4 0xbc000000..0xbc0fffff pa 0xbdf00000..0xbdffffff size 0x100000
DEBUG: [0x0] TEE-CORE:init_mem_map:398: type va 3 0xbc200000..0xbdffffff pa 0xbe200000..0xbfffffff size 0x1e00000
Signed-off-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| c0c5d399 | 01-Oct-2016 |
Jerome Forissier <jerome.forissier@linaro.org> |
Update CHANGELOG.md for 2.2.0
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org
Update CHANGELOG.md for 2.2.0
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (d02) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (hikey) Tested-by: Yan Yan <yan.yan@windriver.com> (imx-mx6qsabrelite) Tested-by: Yan Yan <yan.yan@windriver.com> (imx-mx6qsabresd) Tested-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> (rcar-h3) Tested-by: Joakim Bech <joakim.bech@linaro.org> (rpi3) Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm-b2260) Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm-cannes) Tested-by: Harinarayan Bhatta <harinarayan@ti.com> (ti-dra7xx) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (vexpress-fvp) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (vexpress-juno) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (vexpress-qemu_armv8a) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_virt) Tested-by: Joakim Bech <joakim.bech@linaro.org> (vexpress-qemu_virt) Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> (zynqmp-zcu102)
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| 9a64946c | 07-Oct-2016 |
Etienne Carriere <etienne.carriere@linaro.org> |
plat-stm: introduce b2260 (96boards/cannes)
Flavored 'b2260'. Default no GDB boot, lock pl310, specific DDR size and UART instance.
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2120/
plat-stm: introduce b2260 (96boards/cannes)
Flavored 'b2260'. Default no GDB boot, lock pl310, specific DDR size and UART instance.
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2120/b2260) Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 5c02c1b2 | 07-Oct-2016 |
Etienne Carriere <etienne.carriere@linaro.org> |
plat-stm: fix platform
fix PL310 iomem mapped unsecure. fix rng against nonflat mapping.
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm-b2120) Signed-off-by: Etienne Carriere <etien
plat-stm: fix platform
fix PL310 iomem mapped unsecure. fix rng against nonflat mapping.
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm-b2120) Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| dba1ae65 | 07-Oct-2016 |
Joakim Bech <joakim.bech@linaro.org> |
doc: Update repo xml matrix
- Add qemu_v8_stable.xml, hikey_debian_stable.xml. - Remove "experimental" part for HiKey running Debian, since we are now pointing to the official RPB Linux kernel bra
doc: Update repo xml matrix
- Add qemu_v8_stable.xml, hikey_debian_stable.xml. - Remove "experimental" part for HiKey running Debian, since we are now pointing to the official RPB Linux kernel branch.
Signed-off-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 68b7782a | 05-Oct-2016 |
Joakim Bech <joakim.bech@linaro.org> |
rpi3: refer to new xml-files in documentation
Signed-off-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> |
| f3b8897f | 01-Oct-2016 |
Jerome Forissier <jerome.forissier@linaro.org> |
Add maintainers for D02 and Raspberry Pi3
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@
Add maintainers for D02 and Raspberry Pi3
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 287359f4 | 22-Sep-2016 |
lackan <liang.guanchao@linaro.org> |
crypto: fix incorrect algo passed to cipher.final()
Fix an error in function tee_svc_cipher_update_helper, and add assert in function cipher_final to prevent it being called by an algorithm that is
crypto: fix incorrect algo passed to cipher.final()
Fix an error in function tee_svc_cipher_update_helper, and add assert in function cipher_final to prevent it being called by an algorithm that is not a symmetric cipher.
Signed-off-by: lackan <liang.guanchao@linaro.org> [Reword commit subject] Signed-off-by: Jerome Forissier <jerome.forissier@.linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| a884c935 | 12-Sep-2016 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add support for paging of user TAs
Enables support for paging of user TAs if CFG_PAGED_USER_TA is y
Acked-by: David Brown <david.brown@linaro.org> Tested-by: Jerome Forissier <jerome.forissie
core: add support for paging of user TAs
Enables support for paging of user TAs if CFG_PAGED_USER_TA is y
Acked-by: David Brown <david.brown@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU 7) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| f0f7c8a6 | 12-Sep-2016 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: kern.ld.S: consistent 8 bytes alignment
Replace the last 4 bytes alignment statements with 8 bytes alignment to avoid implicit padding when linking the binary.
Implicit padding following
core: arm: kern.ld.S: consistent 8 bytes alignment
Replace the last 4 bytes alignment statements with 8 bytes alignment to avoid implicit padding when linking the binary.
Implicit padding following the .data section doesn't work with the pager.
Acked-by: David Brown <david.brown@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 96d96148 | 29-Jan-2016 |
Jerome Forissier <jerome.forissier@linaro.org> |
hikey: 32-bit: use -mcpu=cortex-a53 instead of cortex-a15
Use the proper CPU architecture when building 32-bit binaries for HiKey. Note: this triggers a compiler warning: CC out/arm-plat-hik
hikey: 32-bit: use -mcpu=cortex-a53 instead of cortex-a15
Use the proper CPU architecture when building 32-bit binaries for HiKey. Note: this triggers a compiler warning: CC out/arm-plat-hikey/core/tee/tee_svc_cryp.o {standard input}: Assembler messages: {standard input}:632: Warning: IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8 (compiler is gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux). This seems to be harmless and is registered as a compiler bug [1].
[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67591
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| f5f914aa | 27-Sep-2016 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: Add default CFG_CORE_HEAP_SIZE
Adds a CFG_CORE_HEAP_SIZE replacing the defined HEAP_SIZE in each platform_config.h. Default value is defined in mk/config.mk as 64 kB. This is larger than most
core: Add default CFG_CORE_HEAP_SIZE
Adds a CFG_CORE_HEAP_SIZE replacing the defined HEAP_SIZE in each platform_config.h. Default value is defined in mk/config.mk as 64 kB. This is larger than most of the previous values at 24 kB or just above.
Platforms with a previous heap size defined larger than 64 kB overrides the mk/config.mk setting with a $(platform-dir)/conf.mk setting using the previous value.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Hikey pager) Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU v7 pager) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP Aarch32 pager) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 79a90f9b | 27-Sep-2016 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add default CFG_CORE_TZSRAM_EMUL_SIZE
Adds a CFG_CORE_TZSRAM_EMUL_SIZE replacing the previous value directly defined in TZSRAM_SIZE in each platform_config.h. Default value is defined in core/
core: add default CFG_CORE_TZSRAM_EMUL_SIZE
Adds a CFG_CORE_TZSRAM_EMUL_SIZE replacing the previous value directly defined in TZSRAM_SIZE in each platform_config.h. Default value is defined in core/arch/arm/arm.mk as 300 kB. This is larger than most of the previous values.
Platforms with TZSRAM_SIZE defined larger than 200 kB overrides the core/arch/arm/arm.mk setting with a $(platform-dir)/conf.mk setting using the previous value.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 09871a7a | 29-Jul-2016 |
Joakim Bech <joakim.bech@linaro.org> |
scripts: Add tee_bin_parser.py
Signed-off-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> |
| 47805ee4 | 29-Jul-2016 |
Joakim Bech <joakim.bech@linaro.org> |
scripts: gen_hashed_bin.py Python 3.x support
Signed-off-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> |
| ba4f1fc6 | 29-Jul-2016 |
Joakim Bech <joakim.bech@linaro.org> |
scripts: render_font.py for Python 2.x and 3.x
Verified that the output is identical on Python 2.7.12 and Python 3.5.2.
Signed-off-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jerome Foris
scripts: render_font.py for Python 2.x and 3.x
Verified that the output is identical on Python 2.7.12 and Python 3.5.2.
Signed-off-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 6d96f208 | 19-Aug-2016 |
yanyan-wrs <yan.yan@windriver.com> |
Add the i.MX6 Quad SABRE board support (PLATFORM=imx)
Signed-off-by: Yan Yan <yan.yan@windriver.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.for
Add the i.MX6 Quad SABRE board support (PLATFORM=imx)
Signed-off-by: Yan Yan <yan.yan@windriver.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>
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| 147416ca | 07-Sep-2016 |
Matt Ma <matt.ma@linaro.org> |
doc: Add documentation for OP-TEE verification
Gives a brief description on how to enable the verification for OP-TEE using the authentication framework in ATF
Signed-off-by: Matt Ma <matt.ma@linar
doc: Add documentation for OP-TEE verification
Gives a brief description on how to enable the verification for OP-TEE using the authentication framework in ATF
Signed-off-by: Matt Ma <matt.ma@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
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| e3bb8b46 | 20-Sep-2016 |
Joakim Bech <joakim.bech@linaro.org> |
travis: Add RPi3 target
Signed-off-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> |
| 9102ce21 | 19-Sep-2016 |
Jens Wiklander <jens.wiklander@linaro.org> |
syscall storage_obj_seek: fix sign extension
Fixes problem with sign extension (or lack thereof) for the syscall storage_obj_seek. Updates the general rules of arguments for syscalls to use signed 3
syscall storage_obj_seek: fix sign extension
Fixes problem with sign extension (or lack thereof) for the syscall storage_obj_seek. Updates the general rules of arguments for syscalls to use signed 32-bit parameters when a signed parameter is needed.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey) Suggested-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU and FVP) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 983d0211 | 14-Sep-2016 |
Matt Ma <matt.ma@linaro.org> |
ltc: remove test related source files
Test related source files have not been built into OP-TEE image all the time, so we remove them permanently.
Signed-off-by: Matt Ma <matt.ma@linaro.org> Review
ltc: remove test related source files
Test related source files have not been built into OP-TEE image all the time, so we remove them permanently.
Signed-off-by: Matt Ma <matt.ma@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 194d0ae8 | 16-Sep-2016 |
Jerome Forissier <jerome.forissier@linaro.org> |
travis: build all FS code in 64-bit mode
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> |
| a2b0026c | 16-Sep-2016 |
Jerome Forissier <jerome.forissier@linaro.org> |
Fix 64-bit compile error in tee_sql_fs.c
$ make PLATFORM=hikey CFG_SQL_FS=y CFG_ARM64_core=y [snip] core/tee/tee_sql_fs.c: In function ‘sql_fs_read’: core/tee/tee_sql_fs.c:740:41: error: comparison
Fix 64-bit compile error in tee_sql_fs.c
$ make PLATFORM=hikey CFG_SQL_FS=y CFG_ARM64_core=y [snip] core/tee/tee_sql_fs.c: In function ‘sql_fs_read’: core/tee/tee_sql_fs.c:740:41: error: comparison between signed and unsigned integer expressions [-Werror=sign-compare] if ((fdp->pos + len) < len || fdp->pos > fdp->meta.length) ^ cc1: all warnings being treated as errors
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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