core: imx: fix compile error

Error log:
core/arch/arm/plat-imx/conf.mk:26: *** missing separator. Stop.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

core: imx: fix compile error

Error log:
core/arch/arm/plat-imx/conf.mk:26: *** missing separator. Stop.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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.travis.yml: Add Coverity addon

Enables Travis to perform a Coverity build and scan when a push
is made to the coverity_scan branch. In this case, the regular
build script is not necessary and skipp

.travis.yml: Add Coverity addon

Enables Travis to perform a Coverity build and scan when a push
is made to the coverity_scan branch. In this case, the regular
build script is not necessary and skipped to save time.

The Coverity build is currently based on the default qemu
configuration.

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: fix ta_private_vmem support

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: fix support of TA_FLAG_CACHE_MAINTENANCE

Allow loaded TAs to set the property TA_FLAG_CACHE_MAINTENANCE.

TAs are allowed to request cache maintenance operations only on
the memory buffers pas

core: fix support of TA_FLAG_CACHE_MAINTENANCE

Allow loaded TAs to set the property TA_FLAG_CACHE_MAINTENANCE.

TAs are allowed to request cache maintenance operations only on
the memory buffers passed as parameters. They are not allowed to
do cache maintenance on TA private data.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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libutee extension: check-access-right for secure/nonsec permissions

Define TEE_MEMORY_ACCESS_NONSECURE and TEE_MEMORY_ACCESS_SECURE are
extensions of the flag bitfield argument of TEE_CheckMemoryAcc

libutee extension: check-access-right for secure/nonsec permissions

Define TEE_MEMORY_ACCESS_NONSECURE and TEE_MEMORY_ACCESS_SECURE are
extensions of the flag bitfield argument of TEE_CheckMemoryAccessRights().
Once one of these is set, core checks the secure mapping attribute.

Note: if both are set, it's obviously an caller error. Implementation
will return a TEE_ERROR_ACCESS_DENIED.

Include tee_api_defines_extensions.h from tee_internal_api_extensions.h
so that TAs only have to include tee_internal_api_extensions.h to access
extensions resources.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: boot up secondary cores more reliable

Set CORE[x]_RST bit when release secondary cores to make it
more reliable.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere

core: imx: boot up secondary cores more reliable

Set CORE[x]_RST bit when release secondary cores to make it
more reliable.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: imx: switch to use c code for PL310

1. Add a new file imx_pl310.c for arm_cl2_config and arm_cl2_enable.

2. For i.MX6Q, CFG_PL310 is defined and arm_cl2_config is implemented.
In arm_cl2_c

core: imx: switch to use c code for PL310

1. Add a new file imx_pl310.c for arm_cl2_config and arm_cl2_enable.

2. For i.MX6Q, CFG_PL310 is defined and arm_cl2_config is implemented.
In arm_cl2_config, all ways are invalidated, but it does not follow
the rules to wait all ways to be invalidated. So In the following
call to inval_cache_vrange, arm_cl2_cleaninvbypa will trigger SLVERR.

This is because the first invalidation operation not finished in
background, and another invalidation is issued to PL310. So switch
to use arm_cl2_invbyway which will wait until invalidation finished.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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ltc: Fix clear big number in TEE wrapper

Reset a transient object clear datas of this object. For big numbers,
the corresponding method bn_clear reset the underlying struct
mpa_numbase_struct by fil

ltc: Fix clear big number in TEE wrapper

Reset a transient object clear datas of this object. For big numbers,
the corresponding method bn_clear reset the underlying struct
mpa_numbase_struct by filling of zeros its data. However this struct has
metadata, and the call of memset is done on the begin on the structure,
so on the metadata + part of the data, instead of being done only of the
datas. Fix by zero only datas.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Emmanuel MICHEL <emmanuel.michel@st.com> (STM platform)
Signed-off-by: Emmanuel MICHEL <emmanuel.michel@st.com>

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core: fix mapping init debug trace

Before this change, debug trace shows wrong virtual address range.

Confusion comes from the 'struct tee_mmap_region':

va Start address of the virtual

core: fix mapping init debug trace

Before this change, debug trace shows wrong virtual address range.

Confusion comes from the 'struct tee_mmap_region':

va Start address of the virtual 'region' where to map.
Aligned on 'region' alignment constraint.
region_size Byte size of the virtual 'region' where to map.
pa Physical start address of the *mapped* buffer.
size Byte size of the *mapped* buffer.

The virtual start address of the *mapped* buffer is not stored in the
structure. It must be computed.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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core: fix 'flow' traces in pager

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Etienne Carriere <etienne.car

core: fix 'flow' traces in pager

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: keep plat_cpu_reset_early() unpaged

Keep plat_cpu_reset_early() in unpaged area since it needs to be always
available.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signe

core: pager: keep plat_cpu_reset_early() unpaged

Keep plat_cpu_reset_early() in unpaged area since it needs to be always
available.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: FS: rename all tee_fs_rpc_new_ functions

Rename all functions with tee_fs_rpc_new_ prefix to use a tee_fs_rpc_
prefix instead now that all the legacy RPC functions are removed.

Reviewed-by: E

core: FS: rename all tee_fs_rpc_new_ functions

Rename all functions with tee_fs_rpc_new_ prefix to use a tee_fs_rpc_
prefix instead now that all the legacy RPC functions are removed.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: FS: remove unused legacy RPC functions

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: SQL FS: use new RPC transaction functions

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: SQL FS: use new RPC rename function

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: FS: simplify FOP create

As the FOP create always is called with the overwrite flag it can be
simplified. This makes the implementation of create much easier.

Reviewed-by: Etienne Carriere <et

core: FS: simplify FOP create

As the FOP create always is called with the overwrite flag it can be
simplified. This makes the implementation of create much easier.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix virt2phys conversion before core main inits

Before this change, virtual-to-physical address conversion with pager
enable was corrupted until TEE executes its main inits. This change
allow

core: fix virt2phys conversion before core main inits

Before this change, virtual-to-physical address conversion with pager
enable was corrupted until TEE executes its main inits. This change
allow v2p conversion in the TEE RAM during core early inits.

Debug mode is a configuration where v2p are done before core main inits.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (QEMU, b2260)
Tested-by: Joakim Bech <joakim.bech@linaro.org> (QEMU)

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core: REE FS: drop struct block

Drops struct block to keep a buffer to use the same approach as in SQL
FS.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jen

core: REE FS: drop struct block

Drops struct block to keep a buffer to use the same approach as in SQL
FS.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: REE FS: remove block cache

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

mm: use paddr_t to support both 32- and 64-bit arch

Adjust low and high parameter and pool entry type to accurately reflect
architectural sizes and additionally, correct other related uses of uint32

mm: use paddr_t to support both 32- and 64-bit arch

Adjust low and high parameter and pool entry type to accurately reflect
architectural sizes and additionally, correct other related uses of uint32_t
that should be paddr_t.

Signed-off-by: Philip Attfield <opensource@sequiturlabs.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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travis: remove CFG_FS_BLOCK_CACHE

Acked-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: REE FS: use a single file per object

Prior to this commit each persistent object was represented by a
directory with several files. With this commit each persistent object is
represented by a

core: REE FS: use a single file per object

Prior to this commit each persistent object was represented by a
directory with several files. With this commit each persistent object is
represented by a single file instead to simplify the implementation.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core/libutee: perform cleanup for magic "4"

Perform cleanup for magic "4" constant that represents amount of tee
params

Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Etienne Ca

core/libutee: perform cleanup for magic "4"

Perform cleanup for magic "4" constant that represents amount of tee
params

Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: beautify CFG_BOOT_SYNC_CPU in generic_entry_a32.S

convert cpu_is_ready(), wait_primary(), wait_secondary() into
marcos. Prevents dummy empty routines when CFG_BOOT_SYNC_CPU is not set.

Signed

core: beautify CFG_BOOT_SYNC_CPU in generic_entry_a32.S

convert cpu_is_ready(), wait_primary(), wait_secondary() into
marcos. Prevents dummy empty routines when CFG_BOOT_SYNC_CPU is not set.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)

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plat-stm: define default configuration when pager is enable

plat-stm can optionally build with CFG_WITH_PAGER=y. Pager RAM is
defined from CFG_CORE_TZSRAM_EMUL_START and CFG_CORE_TZSRAM_EMUL_SIZE.

plat-stm: define default configuration when pager is enable

plat-stm can optionally build with CFG_WITH_PAGER=y. Pager RAM is
defined from CFG_CORE_TZSRAM_EMUL_START and CFG_CORE_TZSRAM_EMUL_SIZE.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)

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