core: imx: imx6ulevk: handle gic and csu

we use uboot to initialize gic and csu before.
Now switch to let OP-TEE handle them.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <i

core: imx: imx6ulevk: handle gic and csu

we use uboot to initialize gic and csu before.
Now switch to let OP-TEE handle them.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: imx: Drop CONSOLE_UART_PA_BASE

Drop CONSOLE_UART_PA_BASE

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[Rebase on top of master]
Sign

core: arm: imx: Drop CONSOLE_UART_PA_BASE

Drop CONSOLE_UART_PA_BASE

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: mx6ulevk: fix CONSOLE_UART_BASE

Fix CONSOLE_UART_BASE, otherwise we will met panic.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewe

core: imx: mx6ulevk: fix CONSOLE_UART_BASE

Fix CONSOLE_UART_BASE, otherwise we will met panic.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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docs: secure storage: make clear it is insecure by default

https://github.com/OP-TEE/optee_os/issues/1258

Signed-off-by: Andy Green <andy@warmcat.com>
Reviewed-by: Jens Wiklander <jens.wiklander@li

docs: secure storage: make clear it is insecure by default

https://github.com/OP-TEE/optee_os/issues/1258

Signed-off-by: Andy Green <andy@warmcat.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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docs: remove crufty references to removed CFG_ENC_FS


Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Andy Green <andy@warmcat.com>

secure storage: update head message when info->dataSize update

When one invokes TEE_WriteObjectData and write some data
into the secure storage file, the data size of the file
may change, but curren

secure storage: update head message when info->dataSize update

When one invokes TEE_WriteObjectData and write some data
into the secure storage file, the data size of the file
may change, but currently it will not update the head
message in persistent objects. This commit will fix this
problem by updating head message when info->dataSize update.

Signed-off-by: Guanchao Liang <liang.guanchao@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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docs: Add build-essential to prerequisites

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: lpae: deal with unaligned regions

Fixes problem in defined memory regions where physical address isn't
pgdir aligned.

Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Fixes: 0f8333b888f1 (

core: lpae: deal with unaligned regions

Fixes problem in defined memory regions where physical address isn't
pgdir aligned.

Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Fixes: 0f8333b888f1 ("plat-vexpress/qemu: correct DRAM layout")
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu: add core_mmu_divide_block() function

This function divides L1/L2 translation table entry to L2/L3 entries.
It can be used when we need finer mapping than currently possible.

Signed-off-by

core_mmu: add core_mmu_divide_block() function

This function divides L1/L2 translation table entry to L2/L3 entries.
It can be used when we need finer mapping than currently possible.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu_v7: slight refactoring to look like core_mmu_lpae

This patch makes core_mmu_v7.c to look simmilar to core_mmu_lpae.c
- ARMv7-specific definitions was moved from core_mmu_defs.h to .c file

core_mmu_v7: slight refactoring to look like core_mmu_lpae

This patch makes core_mmu_v7.c to look simmilar to core_mmu_lpae.c
- ARMv7-specific definitions was moved from core_mmu_defs.h to .c file
- core_mmu_defs.h was removed, because it stored definitions only for v7
- core_mmu_alloc_l2() now really allocates l2 pages

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu: make type_to_attr() function available globally

This function will be used by shared memory subsystem.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklande

core_mmu: make type_to_attr() function available globally

This function will be used by shared memory subsystem.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu.c: introduce add_va_space function

There can be more that one VA space. But old approach does not support
this because there can't be two VA spaces that begin at PA 0x0.

Signed-off-by: Vol

core_mmu.c: introduce add_va_space function

There can be more that one VA space. But old approach does not support
this because there can't be two VA spaces that begin at PA 0x0.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress/qemu: correct DRAM layout.

There are really more memory in qemu config, than configured in
platform_config.h
Invalid DRAM layout causes core_pbuf_is(CORE_MEM_EXTRAM) to fail
when it sh

plat-vexpress/qemu: correct DRAM layout.

There are really more memory in qemu config, than configured in
platform_config.h
Invalid DRAM layout causes core_pbuf_is(CORE_MEM_EXTRAM) to fail
when it should not.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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stdint.h: add UINTPTR_C macro

This macro can be used when we want to present value that boths acceptable
by C compiller and by ld.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed

stdint.h: add UINTPTR_C macro

This macro can be used when we want to present value that boths acceptable
by C compiller and by ld.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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malloc: use spinlock instead of mutex

Allocation functions are atomic (like linux kernel atomic context),
so mutexes are overkill for them. This change will allow use to use
allocator in atomic cont

malloc: use spinlock instead of mutex

Allocation functions are atomic (like linux kernel atomic context),
so mutexes are overkill for them. This change will allow use to use
allocator in atomic contexts like fast SMC calls or IRQ handlers.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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docs: Fix misspelled TSK

Signed-off-by: Kiwamu Okabe <kiwamu@gmail.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

README: minor fixes

Add additional pre-requisites
Minor fixes of table of contents

Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

plat-ti: Move load address and increase SHMEM

Move and expand the shared memory allocation as suggested
by the comment above the definition. This should be a safe
place and size for all DRA7 based p

plat-ti: Move load address and increase SHMEM

Move and expand the shared memory allocation as suggested
by the comment above the definition. This should be a safe
place and size for all DRA7 based platforms.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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scripts: Allow overwriting the checkpatch.pl location

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@lina

scripts: Allow overwriting the checkpatch.pl location

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-ti: Move console related functions to a separate file

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk

plat-ti: Move console related functions to a separate file

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: Add register size definition for serial8250_uart

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@

drivers: Add register size definition for serial8250_uart

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-ti: Fixed issues with MMU mapping

The UART is in non-secure IO mem, mark it as such. Also map the
non-secure context in-case we are started with the MMU enabled.

Signed-off-by: Harinarayan Bha

plat-ti: Fixed issues with MMU mapping

The UART is in non-secure IO mem, mark it as such. Also map the
non-secure context in-case we are started with the MMU enabled.

Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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docs: General RPi3 documentation cleanup

- Move all links to the end of the document
- Update the information that wasn't up to date any longer.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>

docs: General RPi3 documentation cleanup

- Move all links to the end of the document
- Update the information that wasn't up to date any longer.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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docs: Add instructions for JTAG debugging on RPi3

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk

docs: Add instructions for JTAG debugging on RPi3

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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core: arm: support Xilinx ZYNQ7000 ZC702 (plat-zynq7k)

Signed-off-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wi

core: arm: support Xilinx ZYNQ7000 ZC702 (plat-zynq7k)

Signed-off-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...