History log of /optee_os/ (Results 7151 – 7175 of 8382)
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c640d6ef15-Nov-2016 Andrew F. Davis <afd@ti.com>

plat-ti: Enable GIC driver support for DRA7xx

The DRA7xx platform contains a standard GICv2. Enable this driver.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklan

plat-ti: Enable GIC driver support for DRA7xx

The DRA7xx platform contains a standard GICv2. Enable this driver.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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cb0b595413-Dec-2016 Jens Wiklander <jens.wiklander@linaro.org>

core: add pseudo TA for socket

Adds a pseudo TA sockets using tee-supplicant.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (

core: add pseudo TA for socket

Adds a pseudo TA sockets using tee-supplicant.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260 pager=y/n)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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a32a96ed13-Dec-2016 Jens Wiklander <jens.wiklander@linaro.org>

libutee: add TEE iSocket interface and implementation

Adds TEE iSocket interface and corresponding user space implementation
for TCP and UDP. A pseudo TA is defined for interaction with OP-TEE
Core.

libutee: add TEE iSocket interface and implementation

Adds TEE iSocket interface and corresponding user space implementation
for TCP and UDP. A pseudo TA is defined for interaction with OP-TEE
Core.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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a974e70917-Feb-2017 Etienne Carriere <etienne.carriere@linaro.org>

documentation: expand contractions

Contractions are better avoided in written documentation unless
they really help one to understand the documentation content.

Signed-off-by: Etienne Carriere <eti

documentation: expand contractions

Contractions are better avoided in written documentation unless
they really help one to understand the documentation content.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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1487bacf17-Feb-2017 Etienne Carriere <etienne.carriere@linaro.org>

documentation: fix table of content

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

1a106e8e17-Feb-2017 Etienne Carriere <etienne.carriere@linaro.org>

documentation: replace OP-TEE OS with OP-TEE core

Strictly speaking, OP-TEE OS refers to the secure services provided
by both the privilege secure layer (OP-TEE 'core') and the userland
services (OP

documentation: replace OP-TEE OS with OP-TEE core

Strictly speaking, OP-TEE OS refers to the secure services provided
by both the privilege secure layer (OP-TEE 'core') and the userland
services (OP-TEE libutee plus few other libraries, eventually also TAs).

This change updates documentation to replace 'OS' with 'core' where
confusion between OS and 'core' is to be avoided and only the OPTEE
'core' is referred, in few words, where 'core' shall be distinguish from
userland components (libraries and/or TAs).

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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cc4e442517-Feb-2017 Etienne Carriere <etienne.carriere@linaro.org>

documentation: fix pseudo-TA description

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

2818e64517-Feb-2017 Etienne Carriere <etienne.carriere@st.com>

core: fix traces in selftest pseudo TA

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissi

core: fix traces in selftest pseudo TA

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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1cb254df17-Feb-2017 Etienne Carriere <etienne.carriere@st.com>

core: allow pseudo TA to not define some handlers

Pseudo TAs that do not need to handle creation, destruction,
session opening and closure do not need to define a handler
for that.

Update pseudo TA

core: allow pseudo TA to not define some handlers

Pseudo TAs that do not need to handle creation, destruction,
session opening and closure do not need to define a handler
for that.

Update pseudo TAs where such handlers at not really useful.
Keep the handlers for the selftest pseudo TA for its traces.


Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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6fded82e17-Feb-2017 Etienne Carriere <etienne.carriere@st.com>

core: allow pseudo TAs to define properties

Before this change, pseudo TAs only supported the multi-session
property. This change allows pseudo TAs to define their expected
properties.

This change

core: allow pseudo TAs to define properties

Before this change, pseudo TAs only supported the multi-session
property. This change allows pseudo TAs to define their expected
properties.

This change will be required for the secure data path (SDP) support.
It allows a TA to be invoked with parameters referring to SDP
memory buffers.

During core init, the pseudo TA support verifies that all registered
pseudo TAs conforms with some It allows core to nicely panic if a
pseudo TA was badly declared, including UUID overlapping between
pseudo TAs.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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4d16894119-Oct-2016 Andrew F. Davis <afd@ti.com>

drivers: Add TRNG driver for DRA7

Add driver for the True Random Number Generator (TRNG) available
on DRA7xx platforms.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Joakim Bech <joakim.

drivers: Add TRNG driver for DRA7

Add driver for the True Random Number Generator (TRNG) available
on DRA7xx platforms.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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933a11e019-Dec-2016 Andrew F. Davis <afd@ti.com>

libutils: Add GENMASK_{32,64} helper macros

Allow defining a bitmask using first and last bits.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

70aa17b814-Feb-2017 Zhizhou Zhang <zhizhouzhang@asrmicro.com>

core: mm: fix map_pa2va()'s bad behavior

map->region_size is `unsigned'. In 64-bit machine,
~((vaddr_t)map->region_size - 1)) will discard high
32-bit. results wrong va value.

Signed-off-by: Zhizho

core: mm: fix map_pa2va()'s bad behavior

map->region_size is `unsigned'. In 64-bit machine,
~((vaddr_t)map->region_size - 1)) will discard high
32-bit. results wrong va value.

Signed-off-by: Zhizhou Zhang <zhizhouzhang@asrmicro.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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09eb522b14-Feb-2017 Zhizhou Zhang <zhizhouzhang@asrmicro.com>

core: arm64: make exception vector 11-bit aligned

bit 0 to bit 10 in VBAR_EL1 is RES0. We should not rely on
RES0 values.

Signed-off-by: Zhizhou Zhang <zhizhouzhang@asrmicro.com>
Reviewed-by: Jens

core: arm64: make exception vector 11-bit aligned

bit 0 to bit 10 in VBAR_EL1 is RES0. We should not rely on
RES0 values.

Signed-off-by: Zhizhou Zhang <zhizhouzhang@asrmicro.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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b36e639b14-Feb-2017 Zhizhou Zhang <zhizhouzhang@asrmicro.com>

core: don't assume VA address size to 32-bit

For some board's PA may larger than 32-bit, in order to
create identity memory mapping, we should enlarge TCR.T0SZ.
Rename ADDR_SPACE_SIZE to CFG_LPAE_AD

core: don't assume VA address size to 32-bit

For some board's PA may larger than 32-bit, in order to
create identity memory mapping, we should enlarge TCR.T0SZ.
Rename ADDR_SPACE_SIZE to CFG_LPAE_ADDR_SPACE_SIZE, and move
the config entry to core/arch/arm/arm.mk.

Signed-off-by: Zhizhou Zhang <zhizhouzhang@asrmicro.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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1bb9094711-Feb-2017 Sunny Kuo <sunnychingk@gmail.com>

core: fix phys_to_virt() in thread_std_smc_entry()

enum tee_core_memtypes (MEM_AREA_NSEC_SHM) is required by
phys_to_virt(), rather than enum buf_is_attr (CORE_MEM_NSEC_SHM)

Signed-off-by: Sunny Ku

core: fix phys_to_virt() in thread_std_smc_entry()

enum tee_core_memtypes (MEM_AREA_NSEC_SHM) is required by
phys_to_virt(), rather than enum buf_is_attr (CORE_MEM_NSEC_SHM)

Signed-off-by: Sunny Kuo <sunnychingk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
[jf: update commit message with exact function/type names]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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42fb5b2e13-Feb-2017 Etienne Carriere <etienne.carriere@linaro.org>

rename 'static TA' into 'pseudo TA'

This renaming prevents confusion of what is a static TA: static
TAs are NOT Trusted Application operating at OP-TEE core privilege
execution level. There are rath

rename 'static TA' into 'pseudo TA'

This renaming prevents confusion of what is a static TA: static
TAs are NOT Trusted Application operating at OP-TEE core privilege
execution level. There are rather OP-TEE core services that offer
an invocation API based on GP TEE specified invocation API:
open session, invoke command and close session.

This change renames all 'static TA' references into 'pseudo TA'
references.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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84a0627708-Feb-2017 Sid-Ali Teir <git.syedelec@gmail.com>

docs: update README

- Fixed redirection link to kernel coding style
- Fixed broken platform links
- Fixed level header for "Introduction"

Signed-off-by: Sid-Ali Teir <teir.sidali@gmail.com>
Reviewe

docs: update README

- Fixed redirection link to kernel coding style
- Fixed broken platform links
- Fixed level header for "Introduction"

Signed-off-by: Sid-Ali Teir <teir.sidali@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: minor reformatting of commit comment, rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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d6adcd2b08-Feb-2017 Jerome Forissier <jerome.forissier@linaro.org>

core: do not assume GNU awk is available

The rshift(), strtonum() and and() functions are GNU extensions to awk.
Therefore, the build will fail if another variant of awk is installed
on the build sy

core: do not assume GNU awk is available

The rshift(), strtonum() and and() functions are GNU extensions to awk.
Therefore, the build will fail if another variant of awk is installed
on the build system.
Replace the awk calls with bash arithmetic to avoid any issues. We know
we can rely on the shell being bash, since the main Makefile has
SHELL = /bin/bash.

Fixes: aa4cc147a462 ("core: fix build error with large tee-init_load_addr")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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91f6d5a708-Feb-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: arm: pager: bugfix linking

Fixes problem when linking and mobj_phys_get_pa() and mobj_mm_get_pa()
ends up in the paged region instead of the unpaged as expected.
Unfortunately the KEEP_PAGER()

core: arm: pager: bugfix linking

Fixes problem when linking and mobj_phys_get_pa() and mobj_mm_get_pa()
ends up in the paged region instead of the unpaged as expected.
Unfortunately the KEEP_PAGER() macro used iwth these functions when
compiling for AArch64 triggers an assert in the linker so it has to be
guarded with #ifndef ARM64.

Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey, pager, GP)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (qemu_virt, b2260, pager, GP)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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5465e89f08-Feb-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: bugfix flush_ctx_range_from_list()

Fixes missing NULL check in flush_ctx_range_from_list() needed
when the entire pgt list is emptied.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.o

core: bugfix flush_ctx_range_from_list()

Fixes missing NULL check in flush_ctx_range_from_list() needed
when the entire pgt list is emptied.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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db28cbeb07-Feb-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: bugfix tee_pager_rem_uta_region()

Prior to this patch tee_pager_rem_uta_region() just removed a matching
area without proper unregistration. This patch fixes that by looking up
all physical pa

core: bugfix tee_pager_rem_uta_region()

Prior to this patch tee_pager_rem_uta_region() just removed a matching
area without proper unregistration. This patch fixes that by looking up
all physical pages that may use the area and frees the page.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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e9914d5807-Feb-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: bugfix tee_mmu_rem_rwmem()

Prior to this patch tee_mmu_rem_rwmem() checked that the size of the
supplied mobj matches the size of the region entry. Since a mobj may
have any size and region en

core: bugfix tee_mmu_rem_rwmem()

Prior to this patch tee_mmu_rem_rwmem() checked that the size of the
supplied mobj matches the size of the region entry. Since a mobj may
have any size and region entries always are page or page directory
sized, region entries that should have been removed were not. This patch
fixes that by only checking that mobj and va matches the region entry.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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30a4433607-Feb-2017 Jerome Forissier <jerome.forissier@linaro.org>

make clean: don't fail on non-empty directory

"make clean" may report errors when trying to clean with different
configuration values than the ones used during the build. For instance:

$ make -s CF

make clean: don't fail on non-empty directory

"make clean" may report errors when trying to clean with different
configuration values than the ones used during the build. For instance:

$ make -s CFG_RPMB_FS=y
$ make clean
CLEAN out/arm-plat-vexpress
rmdir: failed to remove 'out/arm-plat-vexpress/core/tee': Directory not empty
rmdir: failed to remove 'out/arm-plat-vexpress/core': Directory not empty
rmdir: failed to remove 'out/arm-plat-vexpress': Directory not empty
Makefile:88: recipe for target 'clean' failed
make: *** [clean] Error 1

The clean command should not fail, since the build tree was properly
cleaned for the requested configuration. Fix this by using
'rmdir --ignore-fail-on-non-empty'.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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aa4cc14706-Feb-2017 Zhizhou Zhang <zhizhouzhang@asrmicro.com>

core: fix build error with large tee-init_load_addr

If tee-init_load_addr is higher than 0xffffffff. building failed with:

Traceback (most recent call last):
File "./scripts/gen_hashed_bin.py", l

core: fix build error with large tee-init_load_addr

If tee-init_load_addr is higher than 0xffffffff. building failed with:

Traceback (most recent call last):
File "./scripts/gen_hashed_bin.py", line 148, in <module>
main()
File "./scripts/gen_hashed_bin.py", line 132, in main
write_header(outf, 0, args, 0)
File "./scripts/gen_hashed_bin.py", line 44, in write_header
args.init_mem_usage, paged_size))
struct.error: 'I' format requires 0 <= number <= 4294967295
make: *** [out/arm-plat-vexpress/core/tee.bin] Error 1
make: Leaving directory `/home/zh/work/github/optee_os'

Signed-off-by: Zhizhou Zhang <zhizhouzhang@asrmicro.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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