Fix ROUNDUP()/ROUNDDOWN() macros

Fixes the ROUNDUP()/ROUNDDOWN() macros to mask internally with a bitmask
that is of the same size as the value that is to be rounded. Without
this patch the mask use

Fix ROUNDUP()/ROUNDDOWN() macros

Fixes the ROUNDUP()/ROUNDDOWN() macros to mask internally with a bitmask
that is of the same size as the value that is to be rounded. Without
this patch the mask uses the size of the type of the @size parameter,
which can differ and give wrong result.

Reported-by: Zhizhou Zhang <zhizhouzhang@asrmicro.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Take some GP types into account when running patch check tool

When running checkpatch on the OP-TEE code, for instance during the
Travis checks, it happens that we get false warnings and errors caus

Take some GP types into account when running patch check tool

When running checkpatch on the OP-TEE code, for instance during the
Travis checks, it happens that we get false warnings and errors caused
by the use of GlobalPlatform typedefs. In the following example, the
patch introduces pointers to functions returning TEE_Result, but
checkpatch won't accept it as a valid type:

$ ./scripts/checkpatch.sh d776721 | tail -1
total: 1 errors, 5 warnings, 555 lines checked

To address such issues, declare our custom types in a local file
(typedefs.checkpatch) and use the new --typedefsfile option provided by
checkpatch.pl.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add interface to load user TAs

Some use cases may require custom load and verification methods for
user-mode Trusted Applications. Introduce struct user_ta_store_ops with
open(), get_size(), r

core: add interface to load user TAs

Some use cases may require custom load and verification methods for
user-mode Trusted Applications. Introduce struct user_ta_store_ops with
open(), get_size(), read() and close() functions to abstract these
tasks from the ELF loader code. Do the communication with
tee-supplicant as well as the hashing and signature verification of the
TA binary in core/arch/arm/kernel/ree_fs_ta.c, which may be disabled
and replaced by a different implementation if need be.

CC: Zeng Tao <prime.zeng@hisilicon.com>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey, QEMU)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: Enable interruptions on i.MX6

Signed-off-by: Mathieu Briand <mbriand@witekio.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Yan Yan <yan.yan@windriver.com>

core: mm: add missing entry in teecore_memtype_name()

teecore_memtype_name() does not handle MEM_AREA_SHM_VASPACE. Add it.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by:

core: mm: add missing entry in teecore_memtype_name()

teecore_memtype_name() does not handle MEM_AREA_SHM_VASPACE. Add it.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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The other bits in GICD_CTLR should not be touched

The gic_init() function enables secure and non-secure group1
interrupts in GICD_CTLR register. But the other bits should
not be modified to avoid `U

The other bits in GICD_CTLR should not be touched

The gic_init() function enables secure and non-secure group1
interrupts in GICD_CTLR register. But the other bits should
not be modified to avoid `UNPREDICTABLE` behaviours as per ARM
GICv3 specification.

Signed-off-by: David Wang <david.wang@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: minor edits to commit message]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-ti: Add secure paging support for DRA7xx/AM57xx

Add definitions for secure SRAM and DRAM space for builds with
CFG_WITH_PAGER enabled.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jen

plat-ti: Add secure paging support for DRA7xx/AM57xx

Add definitions for secure SRAM and DRAM space for builds with
CFG_WITH_PAGER enabled.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-ti: Remove duplicate SECRAM memory definition

After removing DEVICEx_TYPE/_PA_BASE/_SIZE support the definition
for SECRAM was moved to main.c, but we had already made this move,
remove the dup

plat-ti: Remove duplicate SECRAM memory definition

After removing DEVICEx_TYPE/_PA_BASE/_SIZE support the definition
for SECRAM was moved to main.c, but we had already made this move,
remove the duplicate definition.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu: add page map/unmap functions

This function allows to map list of physical pages to specified virtual
memory address.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by:

core_mmu: add page map/unmap functions

This function allows to map list of physical pages to specified virtual
memory address.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: remove braces {} around single statement block]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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mm: add new VA region for dynamic shared buffers

This region will be used later to dynamically map shared buffers
provided by Normal World.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>

mm: add new VA region for dynamic shared buffers

This region will be used later to dynamically map shared buffers
provided by Normal World.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix build with DEBUG=y and LOG_LEVEL=0

Fix build issue with CFG_TEE_CORE_DEBUG=y and CFG_TEE_CORE_LOG_LEVEL=0.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jens Wikl

core: fix build with DEBUG=y and LOG_LEVEL=0

Fix build issue with CFG_TEE_CORE_DEBUG=y and CFG_TEE_CORE_LOG_LEVEL=0.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: generic boot: dt: switch console to /secure-chosen/stdout-path

If CFG_DT=y, check the Device Tree's /secure-chosen node and look for
the stdout-path property. Adjust the console output ac

core: arm: generic boot: dt: switch console to /secure-chosen/stdout-path

If CFG_DT=y, check the Device Tree's /secure-chosen node and look for
the stdout-path property. Adjust the console output accordingly.
The DT bindings for this property have been proposed on the LKML [1].

[1] https://www.spinics.net/lists/arm-kernel/msg566034.html

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU)
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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pl011: dt: Add DT support

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro

pl011: dt: Add DT support

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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dt: Introduce struct serial_driver

Add struct serial_driver which will be useful to UART drivers that
want to create devices from a DT node.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro

dt: Introduce struct serial_driver

Add struct serial_driver which will be useful to UART drivers that
want to create devices from a DT node.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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dt: Add dt_map_dev()

Maps a device into memory from its FDT node.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-

dt: Add dt_map_dev()

Maps a device into memory from its FDT node.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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dt: Add FDT manipulation functions

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wikland

dt: Add FDT manipulation functions

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: introduce struct dt_driver

When CFG_DT=y, a linker section is created (.rodata.dtdrv) to hold all
the DT-compatible drivers. The table can later be queried at runtime.
Some manipulation functi

core: introduce struct dt_driver

When CFG_DT=y, a linker section is created (.rodata.dtdrv) to hold all
the DT-compatible drivers. The table can later be queried at runtime.
Some manipulation functions are exported in <kernel/dt.h>.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: dt: use fdt_address_cells() and fdt_size_cells()

Use the functions provided by libfdt instead of our own.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Ca

core: dt: use fdt_address_cells() and fdt_size_cells()

Use the functions provided by libfdt instead of our own.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix non-LPAE page mapped static mapping

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: fix test against end address of core virtual memory

Fix the first argument of the ROUNDUP() that should be 'map->va' instead
of 'va' which is the lowest virtual address mapped.

'va_max' is re

core: fix test against end address of core virtual memory

Fix the first argument of the ROUNDUP() that should be 'map->va' instead
of 'va' which is the lowest virtual address mapped.

'va_max' is renamed 'end' to help code fitting in 80 char lines.

Fixes: aa2ab38be0aa (core: more flexible static memory mapping)
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Remove SQL-FS

With recent developments in REE-FS SQL-FS has become redundant. This
patch removes SQL-FS.

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jerome Forissier <jerome.forissi

Remove SQL-FS

With recent developments in REE-FS SQL-FS has become redundant. This
patch removes SQL-FS.

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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crypto: don't check hash size when the main algorithm is ECDSA

syscall_asymm_verify() (and therefore TEE_AsymmetricVerifyDigest())
incorrectly assumes that the hash algorithm is SHA1 when the main
a

crypto: don't check hash size when the main algorithm is ECDSA

syscall_asymm_verify() (and therefore TEE_AsymmetricVerifyDigest())
incorrectly assumes that the hash algorithm is SHA1 when the main
algorithm is ECDSA, and will panic the TA if the hash size is not set
accordingly. This behavior does not comply with the TEE Internal Core
API v1.1, which states:

"Where a hash algorithm is specified in the algorithm, digestLen SHALL
be equal to the digest length of this hash algorithm".

For TEE_ALG_ECDSA_P192, TEE_ALG_ECDSA_P224, TEE_ALG_ECDSA_P256,
TEE_ALG_ECDSA_P384 and TEE_ALG_ECDSA_P521, no hash algorithm is
specified, and so we must not restrict the hash size to any specific
value.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reported-by: Henrik Andersson <Henrik.Andersson@se.bosch.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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plat-imx: use the mov_imm macro instead of movw/movt

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wikla

plat-imx: use the mov_imm macro instead of movw/movt

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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am57xx: fix build error

Fix "#elif with no expression" error when building with ti-am57xx flavor
Add am57xx to .travic.yml as supported platform

Reviewed-by: Jerome Forissier <jerome.forissier@lina

am57xx: fix build error

Fix "#elif with no expression" error when building with ti-am57xx flavor
Add am57xx to .travic.yml as supported platform

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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core: thread: allocate RPC arg data on demand

Delays the RPC arg data allocation until it's needed to avoid doing RPC
when the caller in normal world isn't prepared to handle it.

Reviewed-by: Jerom

core: thread: allocate RPC arg data on demand

Delays the RPC arg data allocation until it's needed to avoid doing RPC
when the caller in normal world isn't prepared to handle it.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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