libutee: puts(): add trailing newline

puts() should print the supplied string and a trailing newline. Fix it
accordingly.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by:

libutee: puts(): add trailing newline

puts() should print the supplied string and a trailing newline. Fix it
accordingly.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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libutee: printf(): remove prefix and other non-standard behavior

Our implementation of printf() does not comply with the standards,
because it adds a prefix to the output and may print truncation
ch

libutee: printf(): remove prefix and other non-standard behavior

Our implementation of printf() does not comply with the standards,
because it adds a prefix to the output and may print truncation
characters. By doing so it becomes inconsistent with puts(). It is a
problem because the compiler has the ability to perform optimizations
and, in some cases, may invoke puts() instead of printf().

Therefore, remove any output that is not strictly specified in the
printf() parameters.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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libutee: provide an implementation of putchar()

Calling printf() from a TA to print a single character results in a
linker error:

39 TEE_Result TA_CreateEntryPoint(void)
40 {
41 pr

libutee: provide an implementation of putchar()

Calling printf() from a TA to print a single character results in a
linker error:

39 TEE_Result TA_CreateEntryPoint(void)
40 {
41 printf(".");
42 /* ... */
43 }

hello_world_ta.o: In function `TA_CreateEntryPoint':
hello_world_ta.c:41: undefined reference to `putchar'

In this case, the compiler has optimized the printf() call into a call
to putchar(), assuming that we have a C library and that it complies to
the relevant standards (so that printf() and putchar() may be used
interchangeably).

One way to fix the issue is to prevent such optimizations by using
-fno-builtin or -ffreestanding, at the cost of slightly larger code
size and possibly reduced performance.

Another option is to simply provide the missing putchar() function. It
is the purpose of this commit.

Reported-by: Zeng Tao <prime.zeng@hisilicon.com>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-rockchip: rk322x: add PSCI system suspend

Support gating clks and power down PLLs.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
A

plat-rockchip: rk322x: add PSCI system suspend

Support gating clks and power down PLLs.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-rockchip: rk322x: add PSCI features

Add currently implemented PSCI functions.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-

plat-rockchip: rk322x: add PSCI features

Add currently implemented PSCI functions.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-rockchip: rk322x: add PSCI version

Improve PSCI version to PSCI_VERSION_1_0.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-b

plat-rockchip: rk322x: add PSCI version

Improve PSCI version to PSCI_VERSION_1_0.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: sm: add PSCI system suspend

Add __weak property for the function, developers
could have their own implementation.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Fori

core: arm: sm: add PSCI system suspend

Add __weak property for the function, developers
could have their own implementation.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: fix overlapping conditions of pagestore load areas

This change copies pagestore remaining part first, from any location to
its target destination before copying pagestore init part to target
d

core: fix overlapping conditions of pagestore load areas

This change copies pagestore remaining part first, from any location to
its target destination before copying pagestore init part to target
destination. This prevents pagestore init copy to corrupt pagestore
remaining part at the location where bootloader loaded it.

As bootloader can load pagestore data anywhere in RAM, it is possible
that it loads it into an area overlapping with the area allocated by
the core to store effective pagestore. To prevent this, use memmove()
to copy the data instead of memcpy().

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32: handle aborts in system mode

Switch to handle aborts in system mode in order to be able to give a
stack trace in case an abort occurs in the abort handler.

In a manner similar to the A

core: arm32: handle aborts in system mode

Switch to handle aborts in system mode in order to be able to give a
stack trace in case an abort occurs in the abort handler.

In a manner similar to the AArch64 implementation are abort and undef
mode stack pointers pointing to the struct thread_core_local of
corresponding cpu.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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ta/ta.mk: add scripts/symbolize.py to TA dev kit

scripts/symbolize.py is useful to TA developers, so add it to the TA
development kit.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

ta/ta.mk: add scripts/symbolize.py to TA dev kit

scripts/symbolize.py is useful to TA developers, so add it to the TA
development kit.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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ta/ta.mk: remove useless calls to $(wildcard)

File names passed to $(wildcard) in ta/mk contain no wildcarding
token and they all exist. Therefore, $(wildcard <file>) is always equal
to <file> and $

ta/ta.mk: remove useless calls to $(wildcard)

File names passed to $(wildcard) in ta/mk contain no wildcarding
token and they all exist. Therefore, $(wildcard <file>) is always equal
to <file> and $(wildcard) may be omitted.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: optimize tee_pager_handle_fault()

Optimizes tee_pager_handle_fault() by using ICACHE_AREA_INVALIDATE
instead of ICACHE_INVALIDATE.

Reviewed-by: Etienne Carriere <etienne.carriere@linar

core: pager: optimize tee_pager_handle_fault()

Optimizes tee_pager_handle_fault() by using ICACHE_AREA_INVALIDATE
instead of ICACHE_INVALIDATE.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: remove unneeded tlb invalidation

Removes one unneeded tlb invalidation when unhiding a page. Since the page
was hidden there's no valid mapping for that entry and tlb entries can't
have

core: pager: remove unneeded tlb invalidation

Removes one unneeded tlb invalidation when unhiding a page. Since the page
was hidden there's no valid mapping for that entry and tlb entries can't
have been created.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey AArch{32,64} pager)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Travis: add -p to mkdir $HOME/bin

Travis are currently migrating Linux distributions from Ubuntu Precise
(12.04) to Trusty (14.04). It seems that $HOME/bin already exists in
the new images, which ca

Travis: add -p to mkdir $HOME/bin

Travis are currently migrating Linux distributions from Ubuntu Precise
(12.04) to Trusty (14.04). It seems that $HOME/bin already exists in
the new images, which causes an error as we do mkdir $HOME/bin.
Add a -p so that the directory creation doesn't fail when bin
exists. This allows the script to run on both Precise and Trusty.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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core: arm: mmu: enable MEM_AREA_TEE_COHERENT

Enable MEM_AREA_TEE_COHERENT with attribute setting to
SECURE/PRWX/NONCACHE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jen

core: arm: mmu: enable MEM_AREA_TEE_COHERENT

Enable MEM_AREA_TEE_COHERENT with attribute setting to
SECURE/PRWX/NONCACHE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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.travis.yml: Add Rockchip RK322X

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

MAINTAINERS.md: Add maintainer for Rockchip RK322X

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

README.md: Add Rockchip RK322X description

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

benchmark: fix core data-abort at address 0x0

Issue reproduces with enabled CFG_TEE_BENCHMARK and in case when
registration of benchmark timestamp buffer failes or isn't performed
(in case if any CA

benchmark: fix core data-abort at address 0x0

Issue reproduces with enabled CFG_TEE_BENCHMARK and in case when
registration of benchmark timestamp buffer failes or isn't performed
(in case if any CA is invoked directly, without using benchmark CA)

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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Add plat-rockchip support

Initial version support for rockchip SoCs.(RK322X and next SoCs).

This patch adds to support the RK322X. It is one of the Rockchip
family SoCs, which is a 4*A7 multi-cores

Add plat-rockchip support

Initial version support for rockchip SoCs.(RK322X and next SoCs).

This patch adds to support the RK322X. It is one of the Rockchip
family SoCs, which is a 4*A7 multi-cores ARM SoCs.

plat-rockchip support features:
1.Support SMP cpu boot up and power down;
2.Support system reset;
3.Support GIC driver initialization.

make PLATFORM=rockchip-rk322x

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add udelay function

Using ARM Generic Timer to support time delay, make sure CNTFRQ
register has been initialized before use.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jero

core: add udelay function

Using ARM Generic Timer to support time delay, make sure CNTFRQ
register has been initialized before use.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: serial8250_uart: use 32-bit accesses to the uart registers

Due to hardware design, some platforms can't access the peripheral IO
registers once a byte(8-bit) but once a word(32-bit). Obviou

drivers: serial8250_uart: use 32-bit accesses to the uart registers

Due to hardware design, some platforms can't access the peripheral IO
registers once a byte(8-bit) but once a word(32-bit). Obviously, using
32-bit accesses to the registers is more flexible for other plaforms
to use serial8250 uart.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org> (serial8250_uart, TI-AM57xx)

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core: arm: boot: fix get_memory

From Power_ePAPR_APPROVED_v1.1.pdf chapter 3.4 Memory node,
there is no address-cells and size-cells property for in
memory node. Memory node only support three prope

core: arm: boot: fix get_memory

From Power_ePAPR_APPROVED_v1.1.pdf chapter 3.4 Memory node,
there is no address-cells and size-cells property for in
memory node. Memory node only support three properties "device_type",
"reg" and "initial-mapped-area".

When prase the memory node, need to use the address/size-cells of
root node.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-d02: enable 64-bit paging

Allow CFG_WITH_PAGER=y when building for D02 in 64-bit mode. In this
case, set CFG_CORE_TZSRAM_EMUL_SIZE to 640 KiB to get reasonable
performance.

| time xt

plat-d02: enable 64-bit paging

Allow CFG_WITH_PAGER=y when building for D02 in 64-bit mode. In this
case, set CFG_CORE_TZSRAM_EMUL_SIZE to 640 KiB to get reasonable
performance.

| time xtest 4002 (s)
---------+--------------------
512 KiB | 16
544 KiB | 6
640 KiB | 0.07

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: mmu: fix core_mmu_add_mapping()

Use dsb_ishst() to make sure the new entry visible before continuing.

A9 Unified main TLB:
supports hardware page table walks to perform look-ups in the L

core: arm: mmu: fix core_mmu_add_mapping()

Use dsb_ishst() to make sure the new entry visible before continuing.

A9 Unified main TLB:
supports hardware page table walks to perform look-ups in the L1 data
cache

To A7 and A15, they both support coherent walk, see ID_MMFR3:
Updates to the translation tables do not require a clean to the point of
unification to ensure visibility by subsequent translation table walks

Note: I did not find doc talking coherent walk for A8, so A8 may need
cached flushed when update TLB?

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: minor edits to commit message]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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