docs: add a GitHub pull request template

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

docs: add a GitHub issue template

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: tee_mmu: avoid resource leak

If calloc fails, need to free the asid bit in g_asid.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: user_ta: use TEE_MMU_UMAP_STACK_IDX

Use TEE_MMU_UMAP_STACK_IDX to replace the number 0.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

plat-ti: Configure and enable Secure Data Path by default

Enable SDP by default on TI platforms and reserve 4 MiB from the end of
the TZDRAM area that is already reserved for OP-TEE and firewalled.

plat-ti: Configure and enable Secure Data Path by default

Enable SDP by default on TI platforms and reserve 4 MiB from the end of
the TZDRAM area that is already reserved for OP-TEE and firewalled.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-ti: Add Suspend/Resume support for AM43xx

When the non-secure world is attempting to suspend it will call into the
secure side using a platform service call. We implement this here in
OP-TEE by

plat-ti: Add Suspend/Resume support for AM43xx

When the non-secure world is attempting to suspend it will call into the
secure side using a platform service call. We implement this here in
OP-TEE by saving the needed secure side registers.

On resume the ROM will restore the secure side to its original
configuration and OP-TEE will be re-entered from its boot reset vector.
Add a check for the resume case and restore the secure registers if we
are resuming.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: thread: clarify syscalls return and panic

Updates comments describing how syscall_sys_return() and syscall_panic()
manages to return from the TA in order to resume execution in OP-TEE OS.

Ack

core: thread: clarify syscalls return and panic

Updates comments describing how syscall_sys_return() and syscall_panic()
manages to return from the TA in order to resume execution in OP-TEE OS.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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qemu_v8: move SHM region

With the current setup, qemu puts initrd in the midst of reserved
SHM region. This confuses linux kernel, because it forbids self
to access that reserved region.
As there ar

qemu_v8: move SHM region

With the current setup, qemu puts initrd in the midst of reserved
SHM region. This confuses linux kernel, because it forbids self
to access that reserved region.
As there are no easy way tell qemu where to put initrd, it is easier
to move SHM in the optee-os.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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README.md: Update TI URLs to product landing pages

Currently we point to an individual SoCs product page, each OP-TEE
flavor works across an entire SoC family, so point the flavor info
to the family

README.md: Update TI URLs to product landing pages

Currently we point to an individual SoCs product page, each OP-TEE
flavor works across an entire SoC family, so point the flavor info
to the family landing page instead.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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TUI: remove frame buffer

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

TUI: remove ps2mouse

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

TUI: remove clcd pl111

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

TUI: remove PL050

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

TUI: remove unused scripts/render_font.py

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-ti: Disable TRNG use on AM43xx

On AM43xx family devices the non-secure side may IDLE hardware IP
that are not in use. This will prevent the correct operation of these
IP on the secure side. Unt

plat-ti: Disable TRNG use on AM43xx

On AM43xx family devices the non-secure side may IDLE hardware IP
that are not in use. This will prevent the correct operation of these
IP on the secure side. Until a solution to share management of IPs is
developed, disable the secure driver for this platform.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-mediatek: Use CFG_CORE_CLUSTER_SHIFT to remove get_core_pos_mpidr()

Use the new CFG_CORE_CLUSTER_SHIFT to remove the platform specific
core_pos() helpers.

Signed-off-by: Andrew F. Davis <afd@t

plat-mediatek: Use CFG_CORE_CLUSTER_SHIFT to remove get_core_pos_mpidr()

Use the new CFG_CORE_CLUSTER_SHIFT to remove the platform specific
core_pos() helpers.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: Make core_pos more generic

The function core_pos() assumes 4 cores per cluster, this may not
be true for all platforms. Define CFG_CORE_CLUSTER_SHIFT to be
=log2(cores/cluster) and allow setti

core: Make core_pos more generic

The function core_pos() assumes 4 cores per cluster, this may not
be true for all platforms. Define CFG_CORE_CLUSTER_SHIFT to be
=log2(cores/cluster) and allow setting this from platform config.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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scripts/gen_ld_sects.py: Explicitly number positional argument specifiers

Before Python 2.7 omitting the positional argument specifier was not
allowed. Some may still be using earlier Python version

scripts/gen_ld_sects.py: Explicitly number positional argument specifiers

Before Python 2.7 omitting the positional argument specifier was not
allowed. Some may still be using earlier Python version where this
will cause build to fail. Fix this here.

Fixes: 5976a0a5b9bf ("core: avoid incremental linking with -gc")
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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libutee: remove Trusted UI code

Removes all the TUI-related code from libutee (lib/libutee/tui), as
well as its dependencies: lib/libpng and lib/libzlib. Two reasons for
this:
1. This is far from b

libutee: remove Trusted UI code

Removes all the TUI-related code from libutee (lib/libutee/tui), as
well as its dependencies: lib/libpng and lib/libzlib. Two reasons for
this:
1. This is far from being a complete and testable TUI implementation.
In other words, it is dead code, more or less.
2. lib/libzlib (version 1.2.8) contains several CVE vulnerabilities.
Even if the code is not used, it may trigger some code analysis tools
and is a problem for some projects.

Reported-by: Jianhui Li <airbak.li@hisilicon.com>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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rpmb: mask off RPV/CRC fields in CID to derive rpmb key

PRV (Product revision) [55:48] and CRC field [7:1] in CID would be
changed when doing eMMC FFU.
It is reasonable to mask off PRV and CRC in CI

rpmb: mask off RPV/CRC fields in CID to derive rpmb key

PRV (Product revision) [55:48] and CRC field [7:1] in CID would be
changed when doing eMMC FFU.
It is reasonable to mask off PRV and CRC in CID when using CID to
derive RPMB key.

Signed-off-by: Peifu Jiang <peifu.jiang@amlogic.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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dts: pass PA of reserved region

config_nsmem() used VA of SHM region. This is wrong and it confused
linux kernel. We need to pass physical address.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gm

dts: pass PA of reserved region

config_nsmem() used VA of SHM region. This is wrong and it confused
linux kernel. We need to pass physical address.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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ci: .shippable.yml: fix _make function

The _make function is supposed to return an error status in case make
fails. For this to happen, we need to use && between commands, not ;.

Fixes: 5da449eaf73

ci: .shippable.yml: fix _make function

The _make function is supposed to return an error status in case make
fails. For this to happen, we need to use && between commands, not ;.

Fixes: 5da449eaf73b ("ci: add .shippable.yml")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: psci: Split PM config from PSCI

Not all platforms need PM when implementing PSCI, also some
platforms may need PM but do not implement PSCI. As PSCI has
no direct dependence on PM, split

core: arm: psci: Split PM config from PSCI

Not all platforms need PM when implementing PSCI, also some
platforms may need PM but do not implement PSCI. As PSCI has
no direct dependence on PM, split these config options.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: fix core_mmu_map_pages()

Adds missing dsb_ishst() at the end of core_mmu_map_pages() needed to
guarantee that changes to translation tables are visible.

Reviewed-by: Etienne Carriere <etienne

core: fix core_mmu_map_pages()

Adds missing dsb_ishst() at the end of core_mmu_map_pages() needed to
guarantee that changes to translation tables are visible.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Stuart Yoder <stuart.yoder@arm.com>
Reported-by: Stuart Yoder <stuart.yoder@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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ci: .shippable.yml: fix commit range

When building a pull request, we want to run checkpatch on each commit
included in the pull request. Unfortunately, it is not what the current
code does, because

ci: .shippable.yml: fix commit range

When building a pull request, we want to run checkpatch on each commit
included in the pull request. Unfortunately, it is not what the current
code does, because $SHIPPABLE_COMMIT_RANGE contains a three-dot
notation such as: <commit>...<commit>. This syntax is interpreted
differently depending on the git command that parses it.

Quoting git help diff:

git diff [--options] <commit> <commit> [--] [<path>...]
This is to view the changes between two arbitrary <commit>.

git diff [--options] <commit>..<commit> [--] [<path>...]
This is synonymous to the previous form.

git diff [--options] <commit>...<commit> [--] [<path>...]
This form is to view the changes on the branch containing and up
to the second <commit>, starting at a common ancestor of both
<commit>.

Quoting git help revisions (documents the format used by git log or
git rev-list):

<rev1>..<rev2>
Include commits that are reachable from <rev2> but exclude those
that are reachable from <rev1>.

<rev1>...<rev2>
Include commits that are reachable from either <rev1> or <rev2>
but exclude those that are reachable from both.

In other words, three dots for git diff is like two dots for git log or
git rev-list. What we need to use with git rev-list is the two dot
notation.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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