core: imx: a7_plat_init: implement get_core_pos_mpidr

Implement get_core_pos_mpidr for A7.
According the DIT0017f_Cortex-A7_Integration_Manual_r0p5,
If the system contains only a single multiprocess

core: imx: a7_plat_init: implement get_core_pos_mpidr

Implement get_core_pos_mpidr for A7.
According the DIT0017f_Cortex-A7_Integration_Manual_r0p5,
If the system contains only a single multiprocessor device,
tie all the CLUSTERID[3:0] to HIGH.
To i.MX family which use A7 core, there is no one contains
more that 4 cores. on i.MX7ULP, there is only one core.
So implement get_core_pos_mpidr to avoid get wrong cpu id.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-imx: pm: generate struct imx7_pm_info offsets automatically

Remove hardcoded defines PM_INFO_MX7_* and generate them at build time
instead.

Signed-off-by: Jerome Forissier <jerome.forissier@li

plat-imx: pm: generate struct imx7_pm_info offsets automatically

Remove hardcoded defines PM_INFO_MX7_* and generate them at build time
instead.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-and-Tested-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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build: introduce asm-defines-y

The Makefile rules that are used to generate a C header file containing
constants for struct offsets etc. are currently in mk/compile.mk. They
are used by core.mk whic

build: introduce asm-defines-y

The Makefile rules that are used to generate a C header file containing
constants for struct offsets etc. are currently in mk/compile.mk. They
are used by core.mk which sets a variable (asm-defines-file) before it
includes compile.mk. This works well for this purpose, but does not
scale to several files.

There is a use case for platform code to be able to use the asm-defines
mechanism, too. Therefore, introduce a variable that can be used in any
sub.mk: asm-defines-y.

In addition, to avoid duplication, the DEFINE and DEFINES macros are
moved to their own header (core/include/gen-asm-defines.h), with the
added benefit that it can be explicitly excluded from the checkpatch
list and thus not generate any warning on the 'DEFINE' macro needing
parentheses.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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build: include <generated/asm-defines.h> instead of <asm-defines.h>

Make it clear that asm-defines.h is not to be found in the sources
since it is generated.

Signed-off-by: Jerome Forissier <jerome

build: include <generated/asm-defines.h> instead of <asm-defines.h>

Make it clear that asm-defines.h is not to be found in the sources
since it is generated.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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ci: .travis.yml: clone stable version (3.0.0)

Due to recent changes in manifest.git and build.git for buildroot
support, it is not possible to build with GCC4.9 anymore. One has
to use the toolchai

ci: .travis.yml: clone stable version (3.0.0)

Due to recent changes in manifest.git and build.git for buildroot
support, it is not possible to build with GCC4.9 anymore. One has
to use the toolchain installed by "make toolchains".

Since we want to keep GCC4.9 for now [1], let's revert to an older,
stable version of the source tree, except for the optee_* projects
which we keep at the tip of their master branch.

[1] Commit 148ea708383e ("ci: .travis.yml: use GCC 4.9")

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mmu: set reserved vaspace size configurable

Signed-off-by: Fangsuo Wu <fangsuowu@asrmicro.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.ca

core: mmu: set reserved vaspace size configurable

Signed-off-by: Fangsuo Wu <fangsuowu@asrmicro.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: mmu: check virtual memory size in memory mapping

Current RES_VASPACE_SIZE is defined as (CORE_MMU_PGDIR_SIZE * 10).
When requests virtual memory size larger than RES_VASPACE_SIZE,
there's no s

core: mmu: check virtual memory size in memory mapping

Current RES_VASPACE_SIZE is defined as (CORE_MMU_PGDIR_SIZE * 10).
When requests virtual memory size larger than RES_VASPACE_SIZE,
there's no size check in core_mmu_add_mapping and the physic memory
out of RES_VASPACE_SIZE is mapped incorrectly.

For example, suppose CORE_MMU_PGDIR_SIZE = 1 << 21, i.e. RES_VASPACE_
SIZE = 20M bytes. When mmap table initilized, dump_mmap_table shows:

E/TC:00 dump_mmap_table:704 type RES_VASPACE va 0x112600000..0x1139fffff pa 0x00000000..0x013fffff size 0x01400000 (pgdir)
E/TC:00 dump_mmap_table:704 type TA_RAM va 0x113a00000..0x1153fffff pa 0x100600000..0x101ffffff size 0x01a00000 (pgdir)
...
E/TC:00 dump_mmap_table:704 type IO_SEC va 0x117400000..0x117dfffff pa 0xc0000000..0xc09fffff size 0x00a00000 (pgdir)

after core_mmu_add_mapping(MEM_AREA_NSEC_SHM, paddr, 0x1a00000) executed:

E/TC:00 dump_mmap_table:704 type RES_VASPACE va 0x114000000..0x1139fffff pa 0x00000000..0xffffffffff9fffff size 0xffffffffffa00000 (pgdir)
E/TC:00 dump_mmap_table:704 type TA_RAM va 0x113a00000..0x1153fffff pa 0x100600000..0x101ffffff size 0x01a00000 (pgdir)
...
E/TC:00 dump_mmap_table:704 type IO_SEC va 0x117400000..0x117dfffff pa 0xc0000000..0xc09fffff size 0x00a00000 (pgdir)
E/TC:00 dump_mmap_table:704 type NSEC_SHM va 0x112600000..0x113ffffff pa 0x102000000..0x1039fffff size 0x01a00000 (pgdir)

There are 2 mistakes in the lattest dumped mmu table:
1. For type RES_VASPACE, the base address 0x114000000 is even smaller
than its end address 0x1139fffff;
2. For type TA_RAM and NSEC_SHM, the virtual memory range 0x113a00000
..0x113ffffff both exists, but the physics memory are different and
virt_to_phys(0x113a00000) always returns 0x100600000.

With this patch, if requested virtual memory size overflows, core_mmu
_add_mapping returns false directly.

Signed-off-by: Fangsuo Wu <fangsuowu@asrmicro.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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MAINTAINERS: Add MAINTAINERS entry for NXP WaARP7

This commit adds two maintainers for this board.

- Peng Fan who has done most of the i.MX7 work.
- Bryan O'Donoghue (me) very happily reusing all o

MAINTAINERS: Add MAINTAINERS entry for NXP WaARP7

This commit adds two maintainers for this board.

- Peng Fan who has done most of the i.MX7 work.
- Bryan O'Donoghue (me) very happily reusing all of Peng's work for WaRP7.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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doc: add NXP WaARP7 to supported platforms

This patch adds the WaRP7 board to the list of supported boads in
README.md.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Pen

doc: add NXP WaARP7 to supported platforms

This patch adds the WaRP7 board to the list of supported boads in
README.md.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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arm: imx: add iMX7S WaARP7 board definition

This patch adds a simple option to select a WaARP7 board build. Existing
code upstream does most of the work here.

Make this board port with:

make PLATF

arm: imx: add iMX7S WaARP7 board definition

This patch adds a simple option to select a WaARP7 board build. Existing
code upstream does most of the work here.

Make this board port with:

make PLATFORM=imx PLATFORM_FLAVOR=mx7swarp7 ARCH=arm CFG_PAGEABLE_ADDR=0
CFG_DT_ADDR=0x83000000 DEBUG=y CFG_TEE_CORE_LOG_LEVEL=1 -j 8

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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core: arm: sm: cleanup license

Cleanup license header to only have
"SPDX-License-Identifier: BSD-2-Clause"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@li

core: arm: sm: cleanup license

Cleanup license header to only have
"SPDX-License-Identifier: BSD-2-Clause"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: imx: cleanup license

Cleanup license header to only have
"SPDX-License-Identifier: BSD-2-Clause"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@s

core: arm: imx: cleanup license

Cleanup license header to only have
"SPDX-License-Identifier: BSD-2-Clause"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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MAINTAINERS: mark Xilinx Zynq UltraScale+ MPSOC as Orphan

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
CC: Sören Brinkmann <soren.brinkmann@xilinx.com>
Reported-by: Joakim Bech <joa

MAINTAINERS: mark Xilinx Zynq UltraScale+ MPSOC as Orphan

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
CC: Sören Brinkmann <soren.brinkmann@xilinx.com>
Reported-by: Joakim Bech <joakim.bech@linaro.org>

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MAINTAINERS: add "THE REST"

Add a new entry to the maintainers list, which should remain the last
one and gives contact information for the overall project maintainers
and main reviewers.

Signed-of

MAINTAINERS: add "THE REST"

Add a new entry to the maintainers list, which should remain the last
one and gives contact information for the overall project maintainers
and main reviewers.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Victor Chong <victor.chong@linaro.org>

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Adopt format of Linux MAINTAINERS file

Our current MAINTAINERS.md file is quite impractical for two common use
cases:

1. Finding the platform maintainer(s) given a file path in the OP-TEE
OS source

Adopt format of Linux MAINTAINERS file

Our current MAINTAINERS.md file is quite impractical for two common use
cases:

1. Finding the platform maintainer(s) given a file path in the OP-TEE
OS source tree;
2. Contacting maintainers via GitHub (such as mentioning them in pull
requests).

To fix this, adopt the Linux format and extend the e-mail address field
to also contain an optional GitHub ID, such as:

John Doe <john.doe@example.com> [@johndoe]

Since the file is not in Markdown format anymore, drop the .md
extension as well.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Volodymyr Babchuk <vlad.babchuk@epam.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Akshay Bhat <akshay.bhat@timesys.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Kevin Peng <kevinp@marvell.com>
Acked-by: Sumit Garg <sumit.garg@nxp.com>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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core: insert memory barrier after write to ns entry context

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Tested-by: Jordan Rhee <jordan

core: insert memory barrier after write to ns entry context

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>

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core/crypto/aes-gcm-ce.c:Remove unused included header file

Remove tomcrypt.h from aes-gcm-ce.c which is unused for it.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wikla

core/crypto/aes-gcm-ce.c:Remove unused included header file

Remove tomcrypt.h from aes-gcm-ce.c which is unused for it.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Edison Ai <edison.ai@arm.com>

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plat-imx: implement psci_features()

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signe

plat-imx: implement psci_features()

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>

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core: fix psci_cpu_on() to use context_id parameter

The PSCI specification requires the context_id parameter to be
passed in r0 when the core jumps to normal world. Some OS's require
this parameter.

core: fix psci_cpu_on() to use context_id parameter

The PSCI specification requires the context_id parameter to be
passed in r0 when the core jumps to normal world. Some OS's require
this parameter.

Tested on IMX6Quad and IMX7Dual.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>

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core: add ddr overall register

register_ddr() is used to add overall DDR address range.
SDP memories, static SHM, secure DDR and so on need to fix the
problem that intersect with the overall DDR.

R

core: add ddr overall register

register_ddr() is used to add overall DDR address range.
SDP memories, static SHM, secure DDR and so on need to fix the
problem that intersect with the overall DDR.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Edison Ai <edison.ai@arm.com>

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core: rename register_nsec_ddr() to register_dynamic_shm()

register_nsec_ddr() is actually only used to register dynamic physically
non-contiguous SHM, rename it to register_dynamic_shm() will be mo

core: rename register_nsec_ddr() to register_dynamic_shm()

register_nsec_ddr() is actually only used to register dynamic physically
non-contiguous SHM, rename it to register_dynamic_shm() will be more
clear.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Edison Ai <edison.ai@arm.com>

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checkpatch_inc.sh: exclude files with inline assembly

checkpatch.pl produces false errors when given files with inline
assembly [1]. It is best to skip those files entirely.

Link: [1] https://travi

checkpatch_inc.sh: exclude files with inline assembly

checkpatch.pl produces false errors when given files with inline
assembly [1]. It is best to skip those files entirely.

Link: [1] https://travis-ci.org/OP-TEE/optee_os/builds/347435939#L2115
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: select workaround vector in C

Replace the two assembly implementations for selecting the exception
vector with a common C version.

Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Test

core: select workaround vector in C

Replace the two assembly implementations for selecting the exception
vector with a common C version.

Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey, QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm.h: add more MIDR definitions

Adds MIDR_PRIMARY_PART_NUM_MASK and MIDR_IMPLEMENTER_MASK.

Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Signed-off-by: Jens Wiklander <jens.wikland

core: arm.h: add more MIDR definitions

Adds MIDR_PRIMARY_PART_NUM_MASK and MIDR_IMPLEMENTER_MASK.

Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64.h: add read_midr_el1()

Adds read_midr_el1() and the alias read_midr()

Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>