core: arm: mutex: remove owner_id

mutex::owner_id was used for debugging purposes only.
Since commit 8aff6c039ee5 ("core: remove thread_{add,rem}_mutex()"), it is
never set to a valid thread ID anym

core: arm: mutex: remove owner_id

mutex::owner_id was used for debugging purposes only.
Since commit 8aff6c039ee5 ("core: remove thread_{add,rem}_mutex()"), it is
never set to a valid thread ID anymore. Let's just remove the field.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Add TAILQ_ENTRY() to typedefs.checkpatch

When using BSD queues from <sys/queues.h>, a queue entry is declared
with a macro:

TAILQ_ENTRY(type) var;

This makes checkpatch.pl unhappy because the typ

Add TAILQ_ENTRY() to typedefs.checkpatch

When using BSD queues from <sys/queues.h>, a queue entry is declared
with a macro:

TAILQ_ENTRY(type) var;

This makes checkpatch.pl unhappy because the type is unknown:

WARNING: Missing a blank line after declarations
#52: FILE: core/arch/arm/include/mm/tee_pager.h:32:
+ struct pgt *pgt;
+ TAILQ_ENTRY(tee_pager_area) link;

This patch adds a regular expression to typedefs.chackpatch that
matches the macro part, thus fixing the warning.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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gprof: define original mcount APIs inserted by compiler

Simplify gprof implementation via defining original mcount APIs: _mcount
(for aarch64) and __gnu_mcount_nc (for arm) inserted by compiler inst

gprof: define original mcount APIs inserted by compiler

Simplify gprof implementation via defining original mcount APIs: _mcount
(for aarch64) and __gnu_mcount_nc (for arm) inserted by compiler instead
of providing them via __utee_mcount API.

Also remove weak definitions of mcount API that were earlier mandated by
linker script via PROVIDE().

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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Update CHANGELOG.md for 3.5.0

Update CHANGELOG.md and collect Tested-by tags.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Joakim Bech <joakim.bech@linaro.org> (RPi3B)
Tested-by:

Update CHANGELOG.md for 3.5.0

Update CHANGELOG.md and collect Tested-by tags.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Joakim Bech <joakim.bech@linaro.org> (RPi3B)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960, GP)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260, GP)
Tested-by: Peng Fan <peng.fan@nxp.com> (imx6q-sabresd, imx8mm-evk)
Tested-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> (bcm-ns3)
Tested-by: Igor Opaniuk <igor.opaniuk@gmail.com> (Poplar)
Tested-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> (RCAR H3)
Tested-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> (RCAR H3/virtualization)
Tested-by: Akshay Bhat <akshay.bhat@timesys.com> (Atmel SAM)
Tested-by: Sumit Garg <sumit.garg@linaro.org> (Developerbox)
Tested-by: Victor Chong <victor.chong@linaro.org> (HiKey AOSP, HiKey960 AOSP)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU v8)
Tested-by: Joakim Bech <joakim.bech@linaro.org> (QEMU v7)
Tested-by: Joakim Bech <joakim.bech@linaro.org> (FVP)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey)
Tested-by: Andrew F. Davis <afd@ti.com> (DRA7xx, AM43xx, AM57xx, AM65x)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> (WaRP7)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Tested-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> (imx6qsabresd)

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hikey: Add support for UART2

UART2 is console interface provided on the 40-pin Low Speed
Connector in addition to the default UART3.

Reviewed-by: Victor Chong <victor.chong@linaro.org>
Signed-off-b

hikey: Add support for UART2

UART2 is console interface provided on the 40-pin Low Speed
Connector in addition to the default UART3.

Reviewed-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>

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core: user_ta: load_elf(): return meaningful error code

If any error is encountered when the TEE core attempts to load a TA from
TA storage, the next storage is tried and so on until the TA is
succe

core: user_ta: load_elf(): return meaningful error code

If any error is encountered when the TEE core attempts to load a TA from
TA storage, the next storage is tried and so on until the TA is
successfully loaded or there is no more storage to try. In this case, a
generic error code (TEE_ERROR_ITEM_NOT_FOUND) is returned to the caller
of load_elf() and ultimately to the client. This is not super useful,
especially when debug traces are disabled, because the user has no way
to differentiate a true "not found" situation (which might be a
configuration or deployement issue) from an issue with the TA file
itself or an out-of-memory condition etc.

This commit changes the return code of load_elf() to better reflect the
errors. When load_elf_from_store() returns TEE_ERROR_ITEM_NOT_FOUND or
TEE_ERROR_STORAGE_NOT_AVAILABLE, the next storage is tried.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: bcm_gpio: add IPROC GPIO driver

low level driver for Broadcom IPROC GPIO controller.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Acked-by: Etienne Carriere <etienne.car

drivers: bcm_gpio: add IPROC GPIO driver

low level driver for Broadcom IPROC GPIO controller.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Victor Chong <victor.chong@linaro.org>

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plat-bcm: update platform configurations

-add more device ranges and definitions.
-fix dynamic shm api.
-cleanup plaform def.
-enable PL022 SPI, bcm HWRNG and bcm SOTP driver.

Acked-by: Etienne Car

plat-bcm: update platform configurations

-add more device ranges and definitions.
-fix dynamic shm api.
-cleanup plaform def.
-enable PL022 SPI, bcm HWRNG and bcm SOTP driver.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>

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core: arm: imx: handle errata 845369

Under very rare timing circumstances, a data corruption might occur on
a dirty cache line that is evicted from the L1 Data Cache due to another
cache line being

core: arm: imx: handle errata 845369

Under very rare timing circumstances, a data corruption might occur on
a dirty cache line that is evicted from the L1 Data Cache due to another
cache line being entirely written.
Configurations affected:
This erratum affects configurations with either:
- One processor if the ACP is present
- Two or more processors

This erratum can be worked round by setting bit[22] of the undocumented
Diagnostic Control Register to 1. This register is encoded as
CP15 c15 0 c0 1. The bit can be written in Secure state only, with the
following.
Read/Modify/Write code sequence:
MRC p15,0,rt,c15,c0,1
ORR rt,rt,#0x00400000
MCR p15,0,rt,c15,c0,1

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>

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core: arm: imx: a9: tune ACTLR

Tune ACTLR. To SLL, the value is 0xE at runtime.
To others, the value should be 0x4F at runtime.
Bit3 will be enabled when enable L2.

The SMP bit for i.MX6SLL needs t

core: arm: imx: a9: tune ACTLR

Tune ACTLR. To SLL, the value is 0xE at runtime.
To others, the value should be 0x4F at runtime.
Bit3 will be enabled when enable L2.

The SMP bit for i.MX6SLL needs to be make ldrex/strex
instruction work properly.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>

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core: arm: imx: a7: set L1 Data prefetch

The default value of L1PCTL field in ACTLR is 0x3, which is
"3 outstanding pre-fetches permitted", the value should not
be override with 0 to decrease the pe

core: arm: imx: a7: set L1 Data prefetch

The default value of L1PCTL field in ACTLR is 0x3, which is
"3 outstanding pre-fetches permitted", the value should not
be override with 0 to decrease the performance.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>

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libmbedtls: preserve mempool usage on reinit

be040a3e949b ("libmbedtls: preserve mempool usage on reinit") from
branch import/mbedtls-2.16.0

Preserve the use_mempool field when reinitializing X in

libmbedtls: preserve mempool usage on reinit

be040a3e949b ("libmbedtls: preserve mempool usage on reinit") from
branch import/mbedtls-2.16.0

Preserve the use_mempool field when reinitializing X in
mbedtls_mpi_read_binary().

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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libmbedtls: mbedtls_mpi_exp_mod() initialize W

ae499f6a39f3 ("libmbedtls: mbedtls_mpi_exp_mod() initialize W") from
branch import/mbedtls-2.16.0

Initialize W using mbedtls_mpi_init_mempool() instea

libmbedtls: mbedtls_mpi_exp_mod() initialize W

ae499f6a39f3 ("libmbedtls: mbedtls_mpi_exp_mod() initialize W") from
branch import/mbedtls-2.16.0

Initialize W using mbedtls_mpi_init_mempool() instead of memset() to
ensure that the temporary variable uses the designated memory pool if
configured.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ltc: fix preallocation of MPI bignums

Fixes the preallocation to make room for the actual content also in
crypto_bignum_allocate() by calling mbedtls_mpi_grow().

Acked-by: Etienne Carriere <e

core: ltc: fix preallocation of MPI bignums

Fixes the preallocation to make room for the actual content also in
crypto_bignum_allocate() by calling mbedtls_mpi_grow().

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: Introduce OPTEE_SMC_GET_THREAD_COUNT

This call should be used to query OP-TEE about number of threads
(basically, CFG_NUM_THREADS build option).

It is introduced after discussion at [1] about

core: Introduce OPTEE_SMC_GET_THREAD_COUNT

This call should be used to query OP-TEE about number of threads
(basically, CFG_NUM_THREADS build option).

It is introduced after discussion at [1] about possibility to read
number of supported threads. It is needed for XEN OP-TEE mediator to
mitigate possible DoS from virtual guest. If XEN knows number of
OP-TEE threads, it can limit number of standard calls from the guest
on own side.

Also, it can be used by optee client driver, to ratelimit number of calls
from its side.

Link: [1] https://lists.xenproject.org/archives/html/xen-devel/2019-01/msg01460.html

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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pl022, pl061: add missing pager constraint on _ops struct

Add KEEP_PAGER() for pl022_ops and pl061_ops structs.

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jens Wiklander <je

pl022, pl061: add missing pager constraint on _ops struct

Add KEEP_PAGER() for pl022_ops and pl061_ops structs.

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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pl022_spi: fix non-trivial typo

read16() was replaced with io_read8() instead of io_read16() so fix it.

Fixes: 918bb3a5 ("core: upgrade from write32() to io_write32() and friends")

Signed-off-by:

pl022_spi: fix non-trivial typo

read16() was replaced with io_read8() instead of io_read16() so fix it.

Fixes: 918bb3a5 ("core: upgrade from write32() to io_write32() and friends")

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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pl022_spi: simplify receive of remaining data

If the expected number of packets are not received during the
transmit+receive cycle, just receive the remaining data after the
cycle if the Receive FIF

pl022_spi: simplify receive of remaining data

If the expected number of packets are not received during the
transmit+receive cycle, just receive the remaining data after the
cycle if the Receive FIFO (SSPSR_RNE) is not empty, without depending
on the busy (SSPSR_BSY) flag, else we might miss reading some data as
indicated in [1].

LINK: [1] https://github.com/OP-TEE/optee_os/issues/1461#issuecomment-306156463

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: storage: set data length after truncation

After truncating a persistent object, update dataSize in the
corresponding TEE_ObjectInfo structure.

Signed-off-by: Christopher Tam <godtamit@google.

core: storage: set data length after truncation

After truncating a persistent object, update dataSize in the
corresponding TEE_ObjectInfo structure.

Signed-off-by: Christopher Tam <godtamit@google.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU, GP)

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core: arm: kern.ld.S: minimize padding between .heap1 and .nozi

When OP-TEE is build with CFG_WITH_LPAE=y, the things stored in the
.nozi section do not need to be aligned on more than 4 KiB. Only t

core: arm: kern.ld.S: minimize padding between .heap1 and .nozi

When OP-TEE is build with CFG_WITH_LPAE=y, the things stored in the
.nozi section do not need to be aligned on more than 4 KiB. Only the
non-LPAE case requires 16 KiB alignment for the L1 page table.

Use an #ifdef to minimize the extra space between .heap1 and .nozi,
thus making the heap size closer to what is requested by
CFG_CORE_HEAP_SIZE. This can be useful when trying to minimize the
size of the TEE core binary, which could otherwise be bigger than
necessary by as much as 12 KiB.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: kern.ld.S: use ABSOLUTE() in some assertions

Symbols defined inside output sections are relative to the section
start. Therefore, when we want to check the actual address, we need
to appl

core: arm: kern.ld.S: use ABSOLUTE() in some assertions

Symbols defined inside output sections are relative to the section
start. Therefore, when we want to check the actual address, we need
to apply the ABSOLUTE() builtin function to the symbol.

Note that symbols defined outside output sections are absolute by
default, and therefore need not be treated the same.

kern.ld.S has two incorrect assertions which can never fail, because
the value that is checked is in fact 0 (since we are at the beginning
of a section in both cases).

Fix the code by adding the missing ABSOLUTE().

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-imx: mx6: add support for the TZC380 to MX6Q

Use the generic RAM layout to configure the TZC380 according to the
device configuration.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutroni

plat-imx: mx6: add support for the TZC380 to MX6Q

Use the generic RAM layout to configure the TZC380 according to the
device configuration.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Peng Fan <peng.fan@nxp.com>

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tzc380: add region auto configuration function

The tzc_auto_configure() function takes an address, a size, the attribute
and a region as arguments. It calculates the fitting tzc380 region
configurat

tzc380: add region auto configuration function

The tzc_auto_configure() function takes an address, a size, the attribute
and a region as arguments. It calculates the fitting tzc380 region
configuration and applies it to the controller.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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tzc380: add function to retrieve action register

The TZC380 IP has an action configuration which defines the action taken
if a region is accessed with the wrong permissions.
Devices do not have to s

tzc380: add function to retrieve action register

The TZC380 IP has an action configuration which defines the action taken
if a region is accessed with the wrong permissions.
Devices do not have to set the action register explicitly, add a
function to retrieve the default configuration.

Signed-off-by: Rouven Czerwinski <rouven@czerwinskis.de>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: bcm_sotp: add SOTP driver

low level driver for Broadcom SOTP controller.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Si

drivers: bcm_sotp: add SOTP driver

low level driver for Broadcom SOTP controller.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Rahul Gupta <rahul.gupta@broadcom.com>
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>

show more ...