core: scmi_server: fix alphabetical order

Fixes alphabetical ordering of CFG_SCPFW_MOD_* configuration switches
in conf.mk and conf-optee-stm32mp1.mk.

Signed-off-by: Etienne Carriere <etienne.carri

core: scmi_server: fix alphabetical order

Fixes alphabetical ordering of CFG_SCPFW_MOD_* configuration switches
in conf.mk and conf-optee-stm32mp1.mk.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: get DDR range from embedded DTB

Find main memory (DDR) physical range(s) from the secure embedded DTB
if not found from the external DT.

Signed-off-by: Etienne Carriere <etienne.carriere

core: arm: get DDR range from embedded DTB

Find main memory (DDR) physical range(s) from the secure embedded DTB
if not found from the external DT.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm32mp2: conf: support Octo-SPI manager driver

Default enable Octo-SPI manager driver on stm32mp2x platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Eti

plat-stm32mp2: conf: support Octo-SPI manager driver

Default enable Octo-SPI manager driver on stm32mp2x platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: enable OSPI1 on stm32mp257f-ev1 board

Enable OSPI1 on stm32mp257f-ev1 board. Therefore, enable ommanager node.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-

dts: stm32: enable OSPI1 on stm32mp257f-ev1 board

Enable OSPI1 on stm32mp257f-ev1 board. Therefore, enable ommanager node.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add ommanager node to stm32mp251.dtsi

Add the Octo-SPI manager node to the stm32mp251.dtsi file. This peripheral
is a low-level interface that manages the pinmux and the multiplexing of

dts: stm32: add ommanager node to stm32mp251.dtsi

Add the Octo-SPI manager node to the stm32mp251.dtsi file. This peripheral
is a low-level interface that manages the pinmux and the multiplexing of
two instances of Octo-SPI interfaces.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_omm: add OSPI Memory Manager driver

This patch adds OSPI Memory Manager driver.
It handles:
- IOM configuration
- OSPIs address mapping
- IOM sub-system firewall configuration

Signed

drivers: stm32_omm: add OSPI Memory Manager driver

This patch adds OSPI Memory Manager driver.
It handles:
- IOM configuration
- OSPIs address mapping
- IOM sub-system firewall configuration

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: sysconfig: add OSPIs address mapping

This patch adds an API to handle OSPIs address mapping.
The different configurations are:
- OSPI1(256 MBytes), OSPI2(unmapped)
- OSPI1(192 MByte

plat-stm32mp2: sysconfig: add OSPIs address mapping

This patch adds an API to handle OSPIs address mapping.
The different configurations are:
- OSPI1(256 MBytes), OSPI2(unmapped)
- OSPI1(192 MBytes), OSPI2(64 MBytes)
- OSPI1(128 MBytes), OSPI2(128 MBytes)
- OSPI1(64 MBytes), OSPI2(192 MBytes)
- OSPI1(unmapped), OSPI2(256 MBytes).

Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add the SYSCFG node in stm32mp251.dtsi

Add the SYSCFG node in the stm32mp251.dtsi file. This allows some devices
to access global system configuration registers.

Signed-off-by: Gatien C

dts: stm32: add the SYSCFG node in stm32mp251.dtsi

Add the SYSCFG node in the stm32mp251.dtsi file. This allows some devices
to access global system configuration registers.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: update LTDC layer numbers on stm32mp2x platforms

On stm32mp2x platforms, according to the reference manual, the LTDC
layers are named L1/2/3, not L0/1/2.

Signed-off-by: Gatien Chevalli

dt-bindings: update LTDC layer numbers on stm32mp2x platforms

On stm32mp2x platforms, according to the reference manual, the LTDC
layers are named L1/2/3, not L0/1/2.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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libmbedtls: fix compilation warning with GCC14 (2)

Cherry-picking commit 7505c3588f44 ("libmbedtls: fix compilation warning
with GCC14") which was lost in commit c3deb3d6f3b1 ("Squashed commit
upgra

libmbedtls: fix compilation warning with GCC14 (2)

Cherry-picking commit 7505c3588f44 ("libmbedtls: fix compilation warning
with GCC14") which was lost in commit c3deb3d6f3b1 ("Squashed commit
upgrading to mbedtls-3.6.3"). It should have been pushed onto the
import/mbedtls-3.6.2 branch when it was accepted in master but that
didn't happen and therefore it was unfortunately left aside when
upgrading. This time it has been applied to import/mbedtls-3.6.3 [1] so
it will hopefully not be forgotten in the next upgrade.

Link: https://github.com/OP-TEE/optee_os/commit/b526c146f87 [1]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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build: support building on ARM64 host

On ARM64 hosts we don't want to set CROSS_COMPILE when building for
arm64. Don't set a fallback value in this case.

Signed-off-by: Casey Connolly <casey.connol

build: support building on ARM64 host

On ARM64 hosts we don't want to set CROSS_COMPILE when building for
arm64. Don't set a fallback value in this case.

Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: mm: Fix VA base for canonical addresses

RISC-V defines the following virtual address rules:
- For Sv39 (39-bit VA), bits 63–39 all equal to bit 38 of VA
- For Sv48 (48-bit VA), bits 63–48 all

riscv: mm: Fix VA base for canonical addresses

RISC-V defines the following virtual address rules:
- For Sv39 (39-bit VA), bits 63–39 all equal to bit 38 of VA
- For Sv48 (48-bit VA), bits 63–48 all equal to bit 47 of VA
- For Sv57 (57-bit VA), bits 63–57 all equal to bit 56 of VA

In other words, the most-significant bits of VA base must be all one if
the highest SvXX address bit of VA is one.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: fix va to index calculation for RV64

On RV64, shifting va is not enough when top bits are
present in the virtual address, e.g. for Sv48, bits
63-48 must be set when bit 47 is set to form a

core: mm: fix va to index calculation for RV64

On RV64, shifting va is not enough when top bits are
present in the virtual address, e.g. for Sv48, bits
63-48 must be set when bit 47 is set to form a valid
virtual address.

In this case, we need to mask the base-level virtual
addresses to clear any extended bits before calculating
the index.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: mm: add per-mapping VA range validation

Replace single maximum VA check with individual VA
range validation for each memory map entry during MMU
initialization, providing earlier detect

core: riscv: mm: add per-mapping VA range validation

Replace single maximum VA check with individual VA
range validation for each memory map entry during MMU
initialization, providing earlier detection of invalid
mappings.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: factor out virtual address range validation to arch code

Move virtual address range validation into architecture-specific
code since different architectures have different constraints on
v

core: mm: factor out virtual address range validation to arch code

Move virtual address range validation into architecture-specific
code since different architectures have different constraints on
valid VA ranges:

- For ARM, addresses must be within the VA width supported by the MMU
- For RISC-V, additional checks are needed on RV64 to ensure addresses
are canonically valid

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: mm: fix map_offset data type

Fix the data type of map_offset to allow storing 64-bit
offset on RV64.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alving

riscv: mm: fix map_offset data type

Fix the data type of map_offset to allow storing 64-bit
offset on RV64.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: refactor ASLR mapping for architecture support

To allow adding RISC-V ASLR support, add arch_aslr_base_addr()
which will be used to apply architecture specific ASLR base
calculation.

Sign

core: mm: refactor ASLR mapping for architecture support

To allow adding RISC-V ASLR support, add arch_aslr_base_addr()
which will be used to apply architecture specific ASLR base
calculation.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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spmc: fix FF-A manifest boot-order handling

According to the official manifest binding documentation [1], all
integer properties must be defined as 32-bit wide DTB properties.
However, the OP-TEE SP

spmc: fix FF-A manifest boot-order handling

According to the official manifest binding documentation [1], all
integer properties must be defined as 32-bit wide DTB properties.
However, the OP-TEE SPMC previously implemented the boot-order property
as a 16-bit value. This patch corrects that inconsistency by adding
support for the correct 32 bit representation while keeping backwards
compatibility.

Recent changes in TF-A’s build tooling have broken support for manifest
files using the "/bits/" width specifier. This update restores
compatibility by eliminating the need to use them.

[1] FF-A Manifest Binding
Link: https://trustedfirmware-a.readthedocs.io/en/v2.12.0/components/ffa-manifest-binding.html

Signed-off-by: Gyorgy Szing <gyorgy.szing@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: stm32_rifsc: fix RIMU configuration parsing

The RIF configuration of the first RIMU was incorrectly parsed over and
over again for each RIMU. Fix this by using the index that represents
the

drivers: stm32_rifsc: fix RIMU configuration parsing

The RIF configuration of the first RIMU was incorrectly parsed over and
over again for each RIMU. Fix this by using the index that represents
the RIMU ID.

Fixes: cd187630b280 ("drivers: add stm32 RIFSC support")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: remove redundant and incorrect parsing of RIMU conf

In case we're not TDCID, we cannot configure RIMUs. Plus, the call was
redundant with the lines above.

Fixes: 471cec144fa3

drivers: stm32_rifsc: remove redundant and incorrect parsing of RIMU conf

In case we're not TDCID, we cannot configure RIMUs. Plus, the call was
redundant with the lines above.

Fixes: 471cec144fa3 ("drivers: stm32_rifsc: update RIFSC as a firewall controller")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_hpdma: implement transient CID0 on AHB errata for HPDMAs

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the comp

drivers: stm32_hpdma: implement transient CID0 on AHB errata for HPDMAs

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compartment
filtering is enabled on RISAB3/4/5, this transient CID0 is interpreted
as a fault access by RISAB3/4/5 which aborts current access and returns
an IAC. Described in section 2.3.21 of errata sheet available here: [1].
Therefore, when CID filtering is enabled on RISAB, we must ban CID0 as
a possible CID value configured for any initiator on the bus.
This avoids a conflict between an initiator holding CID0 and the
transient CID0.

When "st,errata-ahbrisab" is set in the device tree, HPDMA channels cannot
hold the CID0 value on the bus.

Link: https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: implement transient CID0 on AHB errata for RIMUs

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compa

drivers: stm32_rifsc: implement transient CID0 on AHB errata for RIMUs

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compartment
filtering is enabled on RISAB3/4/5, this transient CID0 is interpreted
as a fault access by RISAB3/4/5 which aborts current access and returns
an IAC. Described in section 2.3.21 of errata sheet available here: [1].
Therefore, when CID filtering is enabled on RISAB, we must ban CID0 as
a possible CID value configured for any initiator on the bus.
This avoids a conflict between an initiator holding CID0 and the
transient CID0.

When "st,errata-ahbrisab" is set in the device tree, RIMUs cannot hold
the CID0 value on the bus.

Link: https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_risab: implement transient CID0 on AHB errata for RISAB

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compa

drivers: stm32_risab: implement transient CID0 on AHB errata for RISAB

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compartment
filtering is enabled on RISAB3/4/5, this transient CID0 is interpreted
as a fault access by RISAB3/4/5 which aborts current access and returns
an IAC. Described in section 2.3.21 of errata sheet available here: [1].
Therefore, when CID filtering is enabled on RISAB, we must ban CID0 as
a possible CID value configured for any initiator on the bus.
This avoids a conflict between an initiator holding CID0 and the
transient CID0.

Force authorize CID0 access on RISAB so that it can always access
memories protected by RISABs when the "st,errata-ahbrisab" property is
set in the device tree.

Link: https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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caam: fix compilation when CFG_NXP_CAAM_AE_* are disabled

Similarly to other CAAM modules, define empty function if CAAM AE is
not used, to avoid undefined reference to caam_ae_init().

Signed-off-b

caam: fix compilation when CFG_NXP_CAAM_AE_* are disabled

Similarly to other CAAM modules, define empty function if CAAM AE is
not used, to avoid undefined reference to caam_ae_init().

Signed-off-by: Pavel Löbl <pavel@loebl.cz>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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ci: QEMUv8: check Firmware Handoff

Add a check entry for Arm Firmware Handoff.

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>