scripts: checkpatch_inc.sh: Add CHECKPATCH_OPT for optional arguments

Add new environment variable CHECKPATCH_OPT for configuring common optional
arguments.

In example newer codespell has moved dic

scripts: checkpatch_inc.sh: Add CHECKPATCH_OPT for optional arguments

Add new environment variable CHECKPATCH_OPT for configuring common optional
arguments.

In example newer codespell has moved dictionary to new location.

This allows one to use:

export CHECKPATCH=<path to linux kernel source>/scripts/checkpatch.pl
export CHECKPATCH_OPT=--codespellfile=/usr/lib/python3/dist-packages/codespell_lib/data/dictionary.txt

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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Update CHANGELOG.md for 3.14.0

Update CHANGELOG for 3.14.0 and collect Tested-by tags.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (

Update CHANGELOG.md for 3.14.0

Update CHANGELOG for 3.14.0 and collect Tested-by tags.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Tested-by: Jerome Forissier <jerome@forissier.org> (hikey-hiKey960)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (imx-mx8mqevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1012A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1043A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1046A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1088A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS2088A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LX2160A-RDB)
Tested-by: Jerome Forissier <jerome@forissier.org> (vexpress-qemu_armv8a)
Tested-by: Jerome Forissier <jerome@forissier.org> (vexpress-qemu_virt)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qpsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sllevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ullevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulzevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7dsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7ulpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mmevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mnevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mqevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qmmek)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qxpmek)
Tested-by: Sumit Garg <sumit.garg@linaro.org> (Developerbox)
Tested-by: Jerome Forissier <jerome@forissier.org> (hikey)
Tested-by: Victor Chong <victor.chong@linaro.org> (QEMUv8 AOSP)
Tested-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> (rcar-salvator_m3_2x4g)
Tested-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> (rcar-salvator_m3_2x4g / virt)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_DK2, pkcs11, gp)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_ED1)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_EV1)
Tested-by: Ricardo Salveti <ricardo@foundries.io> (ZynqMP)

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core: plat-ls: ls1012a: Fix GIC offset

The GIC offset for LS1012A is different than the one for
LS1043A and LS1046A.
Fixing for LS1012A

Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Si

core: plat-ls: ls1012a: Fix GIC offset

The GIC offset for LS1012A is different than the one for
LS1043A and LS1046A.
Fixing for LS1012A

Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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Update revision for release tag 3.14.0-rc1

Signed-off-by: Jerome Forissier <jerome@forissier.org>

Revert "libutee: TEE_MACCompareFinal(): panic if input size is too large"

This reverts commit dbb3274a60f0b258fe115ed1678fc569335c0c5d. It turns
out the panic reason cited in the commit ("If input d

Revert "libutee: TEE_MACCompareFinal(): panic if input size is too large"

This reverts commit dbb3274a60f0b258fe115ed1678fc569335c0c5d. It turns
out the panic reason cited in the commit ("If input data exceeds maximum
length for the algorithm") applies to the message only and has nothing
to do with macLen. The same sentence appears elsewhere in the spec where
there is no ambiguity.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: increase CFG_DTB_MAX_SIZE to 256KiB

On stm32mp1 platform the external DTB that may be passed by former
boot stage may overflow the default 64kB of CFG_DTB_MAX_SIZE hence
increase it t

plat-stm32mp1: increase CFG_DTB_MAX_SIZE to 256KiB

On stm32mp1 platform the external DTB that may be passed by former
boot stage may overflow the default 64kB of CFG_DTB_MAX_SIZE hence
increase it to 256kB which is reasonable for that platform.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: fix shres2str_state() prototype

Reported by GCC-10.2 when build plat-stm32mp1 with CFG_TEE_CORE_LOG_LEVEL=3.

core/arch/arm/plat-stm32mp1/shared_resources.c: In function ‘register_per

plat-stm32mp1: fix shres2str_state() prototype

Reported by GCC-10.2 when build plat-stm32mp1 with CFG_TEE_CORE_LOG_LEVEL=3.

core/arch/arm/plat-stm32mp1/shared_resources.c: In function ‘register_periph’:
core/arch/arm/plat-stm32mp1/shared_resources.c:212:24: warning: implicit conversion from ‘enum shres_state’ to ‘enum stm32mp_shres’ [-Wenum-conversion]
212 | shres2str_state(state));
| ^~~~~

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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libutee: TEE_MACCompareFinal(): panic if input size is too large

The GlobalPlatform TEE Internal Core API specification mentions the
following panic reason for TEE_MACCompareFinal(): "if input data

libutee: TEE_MACCompareFinal(): panic if input size is too large

The GlobalPlatform TEE Internal Core API specification mentions the
following panic reason for TEE_MACCompareFinal(): "if input data exceeds
the maximum length for the algorithm". The current code returns
TEE_ERROR_MAC_INVALID instead. Fix this by assigning error code
TEE_ERROR_BAD_PARAMETERS which gets translated into a panic later.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: imx: increase CFG_DTB_MAX_SIZE to 128KiB

On imx6q, imx6qp, imx6dl and imx7d platforms, we get the following error
at boot:

E/TC:0 0 init_external_dt:1099 Invalid Device Tree at 0x18000000: er

core: imx: increase CFG_DTB_MAX_SIZE to 128KiB

On imx6q, imx6qp, imx6dl and imx7d platforms, we get the following error
at boot:

E/TC:0 0 init_external_dt:1099 Invalid Device Tree at 0x18000000: error -3

i.MX device trees compiled with _symbols_ nodes makes DTB bigger than 56KiB.
Increase the CFG_DTB_MAX_SIZE from 56KiB to 128KiB for all imx6 and imx7
platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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ta: pkcs11: Add access check on new object when deriving/unwrapping

Access check is also required on created attributes when
a new object is created when deriving/unwrapping keys.

Reviewed-by: Vesa

ta: pkcs11: Add access check on new object when deriving/unwrapping

Access check is also required on created attributes when
a new object is created when deriving/unwrapping keys.

Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>

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ta: pkcs11: Add support for indirect templates

Add support for handling indirect template - CKA_DERIVE_TEMPLATE
and CKA_UNWRAP_TEMPLATE during key derivation/unwrapping.

Reviewed-by: Vesa Jääskeläi

ta: pkcs11: Add support for indirect templates

Add support for handling indirect template - CKA_DERIVE_TEMPLATE
and CKA_UNWRAP_TEMPLATE during key derivation/unwrapping.

Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>

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ta: pkcs11: Add implementation for unwrapping keys

Add implementation for handling C_UnwrapKey() for mechanisms :
CKM_AES_ECB
CKM_AES_CBC

Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.c

ta: pkcs11: Add implementation for unwrapping keys

Add implementation for handling C_UnwrapKey() for mechanisms :
CKM_AES_ECB
CKM_AES_CBC

Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>

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ta: pkcs11: Add implementation for wrapping keys

Add implementation for handling C_WrapKey() for mechanisms :
CKM_AES_ECB
CKM_AES_CBC

Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>

ta: pkcs11: Add implementation for wrapping keys

Add implementation for handling C_WrapKey() for mechanisms :
CKM_AES_ECB
CKM_AES_CBC

Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>

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ta: pkcs11: Add missing error codes

Some error codes related with wrap, unwrap and random number
API's were missing from the list. These have been added.

Reviewed-by: Vesa Jääskeläinen <vesa.jaaske

ta: pkcs11: Add missing error codes

Some error codes related with wrap, unwrap and random number
API's were missing from the list. These have been added.

Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>

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ta: pkcs11: Allocate command ID's for wrapping/unwrapping keys

Allocate command ID's for C_WrapKey() and C_UnwrapKey().

Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: E

ta: pkcs11: Allocate command ID's for wrapping/unwrapping keys

Allocate command ID's for C_WrapKey() and C_UnwrapKey().

Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>

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plat-marvell: Add support for OcteonTX2 CNF95xx and CN98xx

Add support for OcteonTX2 CNF95xx and CN98xx platforms
from Marvell.

Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Acked-by: Jerom

plat-marvell: Add support for OcteonTX2 CNF95xx and CN98xx

Add support for OcteonTX2 CNF95xx and CN98xx platforms
from Marvell.

Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-marvell: Add support for OcteonTX2 CN96xx SoC

Add support for OcteonTX2 CN96xx SoC from Marvell.

Only tested 64-bit mode with default configurations:

1. Build command
make PLATFORM=marvell-o

plat-marvell: Add support for OcteonTX2 CN96xx SoC

Add support for OcteonTX2 CN96xx SoC from Marvell.

Only tested 64-bit mode with default configurations:

1. Build command
make PLATFORM=marvell-otx2t96
2. Passed xtest

Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: imx_i2c: support i2c4

Extend the driver functionality to support i2c4

Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: De

drivers: imx_i2c: support i2c4

Extend the driver functionality to support i2c4

Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Devendra Devadiga <devendradevadiga01@gmail.com>

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plat-imx: registers: i2c: support i2c4

Add required definitions to support i2c4

Reviewed-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: D

plat-imx: registers: i2c: support i2c4

Add required definitions to support i2c4

Reviewed-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Devendra Devadiga <devendradevadiga01@gmail.com>

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drivers: imx_i2c: fix support for MX8MQ

Add missing config required to enable the support

Reviewed-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Devendra Devadiga <devendradevadiga01

drivers: imx_i2c: fix support for MX8MQ

Add missing config required to enable the support

Reviewed-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Devendra Devadiga <devendradevadiga01@gmail.com>

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plat-imx: registers: imx6: fix i2c3 base address

Fix the base address of the I2C3 controller

Reviewed-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Devendra Devadiga <devendradevadig

plat-imx: registers: imx6: fix i2c3 base address

Fix the base address of the I2C3 controller

Reviewed-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Devendra Devadiga <devendradevadiga01@gmail.com>

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core: plat-ls: generate tee-raw.bin

LS Platforms use RAW OP-TEE binary, but it is not getting
generated by default for platforms.
So added code for generating it by default for LS platforms.

Signed

core: plat-ls: generate tee-raw.bin

LS Platforms use RAW OP-TEE binary, but it is not getting
generated by default for platforms.
So added code for generating it by default for LS platforms.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>

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core: clear temporary stack flag before entering boot_init_primary_late()

boot_init_primary_late() uses the stack of thread 0, so the flag that
indicates usage of the temporary stack must be cleared

core: clear temporary stack flag before entering boot_init_primary_late()

boot_init_primary_late() uses the stack of thread 0, so the flag that
indicates usage of the temporary stack must be cleared in the current
core's thread_core_local structure.

Fixes the following crash when CFG_CORE_DEBUG_CHECK_STACKS=y:

D/TC:0 0 select_vector:1126 SMCCC_ARCH_WORKAROUND_1 (0x80008000) available
D/TC:0 0 select_vector:1128 SMC Workaround for CVE-2017-5715 used
D/TC:0 0 check_stack_limits:370 Stack pointer out of range (0xb7f54fd0)
D/TC:0 0 print_stack_limits:346 tmp [0] 0xb7f57c90..0xb7f584b0
D/TC:0 0 print_stack_limits:346 tmp [1] 0xb7f58ad0..0xb7f592f0
D/TC:0 0 print_stack_limits:346 tmp [2] 0xb7f59910..0xb7f5a130
D/TC:0 0 print_stack_limits:346 tmp [3] 0xb7f5a750..0xb7f5af70
D/TC:0 0 print_stack_limits:351 abt [0] 0xb7f4e710..0xb7f4f330
D/TC:0 0 print_stack_limits:351 abt [1] 0xb7f4f950..0xb7f50570
D/TC:0 0 print_stack_limits:351 abt [2] 0xb7f50b90..0xb7f517b0
D/TC:0 0 print_stack_limits:351 abt [3] 0xb7f51dd0..0xb7f529f0
D/TC:0 0 print_stack_limits:356 thr [0] 0xb7f53030..0xb7f55030
D/TC:0 0 print_stack_limits:356 thr [1] 0xb7f55670..0xb7f57670
E/TC:0 0 Panic at core/arch/arm/kernel/thread.c:372 <check_stack_limits>

Fixes: 59ac3801b756 ("core: split boot_init_primary()")
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: use adr_l to reference stack_tmp_stride

When CFG_NUM_THREADS and/or CFG_TEE_CORE_NB_CORE become large enough,
link errors are reported:

$ make -s CFG_TEE_CORE_NB_CORE=48 CFG_NUM_THREA

core: arm64: use adr_l to reference stack_tmp_stride

When CFG_NUM_THREADS and/or CFG_TEE_CORE_NB_CORE become large enough,
link errors are reported:

$ make -s CFG_TEE_CORE_NB_CORE=48 CFG_NUM_THREADS=48 \
PLATFORM=vexpress-qemu_armv8a
out/arm-plat-vexpress/core/arch/arm/kernel/entry_a64.o: in function `clear_bss':
core/arch/arm/kernel/entry_a64.S:160:(.text._start+0x98): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `stack_tmp_stride' defined in .identity_map.stack_tmp_stride section in out/arm-plat-vexpress/core/arch/arm/kernel/thread.o
out/arm-plat-vexpress/core/arch/arm/kernel/entry_a64.o: in function `cpu_on_handler':
core/arch/arm/kernel/entry_a64.S:443:(.text.cpu_on_handler+0x50): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `stack_tmp_stride' defined in .identity_map.stack_tmp_stride section in out/arm-plat-vexpress/core/arch/arm/kernel/thread.o

Fix the issue by replacing the addr instruction with the adr_l macro.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: entry_a64.S: use adr_l macro instead of open coding

Replace the open-coded adrp + add :lo12: in set_sp with the macro that
does the very same thing (adr_l).

Signed-off-by: Jerome Forissier <j

core: entry_a64.S: use adr_l macro instead of open coding

Replace the open-coded adrp + add :lo12: in set_sp with the macro that
does the very same thing (adr_l).

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...