core: enable FF-A with SPM Core at S-EL2

This enables support for FF-A with SPM Core at S-EL2 in a secure
hypervisor while OP-TEE is running at S-EL1 as a SP.
This configuration is also know as "S-E

core: enable FF-A with SPM Core at S-EL2

This enables support for FF-A with SPM Core at S-EL2 in a secure
hypervisor while OP-TEE is running at S-EL1 as a SP.
This configuration is also know as "S-EL2 SPMC" in the FFA specification.

Compile with CFG_CORE_SEL2_SPMC=y

Note that this is an experimental feature, ABIs etc may have
incompatible changes.

This depends on using the FF-A v4 patchset in the Linux kernel.

Reviewed-by: Jelle Sels <jelle.sels@arm.com>
Co-developed-by: Marc Bonnici <marc.bonnici@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: spmc: FF-A ABI updates

Updates structs and definitions to follow FF-A version 1.0.

Use the special hard coded UUID (486178e0-e7f8-11e3-bc5e-0002a5d5c51b)
for the SP OP-TEE is when compiled fo

core: spmc: FF-A ABI updates

Updates structs and definitions to follow FF-A version 1.0.

Use the special hard coded UUID (486178e0-e7f8-11e3-bc5e-0002a5d5c51b)
for the SP OP-TEE is when compiled for FF-A.

Updates the FF-A OP-TEE message ABI to make room for struct
optee_msg_arg to be used for RPC for OPTEE_FFA_YIELDING_CALL_WITH_ARG.

struct thread_ctx::rpc_arg for the current thread will always hold a
pointer to the struct optee_msg_arg to be used for RPC.

With this allocation of shared memory can be pushed up one layer and be
done via the struct optee_msg_arg so the
OPTEE_FFA_YIELDING_CALL_RETURN_ALLOC_*_SHM and
OPTEE_FFA_YIELDING_CALL_RETURN_FREE_*_SHM can be removed making the FF-A
ABI a bit less complicated.

Changes OPTEE_FFA_UNREGISTER_SHM to be a blocking call instead of a
yielding call.

Removes the unused OPTEE_FFA_YIELDING_CALL_REGISTER_SHM.

Updates the return values from yielding calls to use the TEE_Result
values instead of FF-A one to use the error code from the correct layer.

Defines OPTEE_MSG_FMEM_INVALID_GLOBAL_ID to 0xffffffffffffffffff which
is used as an invalid global id instead of 0.

This is an ABI breakage which must be done in sync with the FF-A v4
patchset in the Linux kernel.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add a4 and a5 to thread_alloc_and_run()

Adds two parameters a4 and a5 to thread_alloc_and_run(),
thread_std_smc_entry() and __thread_std_smc_entry().

Zeroes are passed where the new parameter

core: add a4 and a5 to thread_alloc_and_run()

Adds two parameters a4 and a5 to thread_alloc_and_run(),
thread_std_smc_entry() and __thread_std_smc_entry().

Zeroes are passed where the new parameters are not needed.

This prepares for the next update of the FF-A ABI for OP-TEE where among
other things one more register is used by
OPTEE_FFA_YIELDING_CALL_WITH_ARG.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm64: add read_cntvct()

Adds read_cntvct() to read Counter-timer Virtual Count register.

Note that arm32 already have this function.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-of

arm64: add read_cntvct()

Adds read_cntvct() to read Counter-timer Virtual Count register.

Note that arm32 already have this function.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add thread_smccc()

Adds the assembly function thread_smccc() which loads the first 8
registers with the argument and executes an SMC or HVC instruction as
appropriate. The result in the first

core: add thread_smccc()

Adds the assembly function thread_smccc() which loads the first 8
registers with the argument and executes an SMC or HVC instruction as
appropriate. The result in the first 8 registers is then saved in
the argument struct.

With the new flag CFG_CORE_SEL2_SPMC configures OP-TEE to work with a
SPMC at S-EL2 instead of the dispatcher at EL3. The SMC instruction
should not be used when working with a SPMC, OP-TEE should instead use
the HVC instruction in such a configuration.

Without a SPMC at S-EL2 OP-TEE works with the dispatcher at EL3 with no
changes.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Rename to barrier_read_counter_timer()

Renames barrier_read_cntpct() to barrier_read_counter_timer() to use a
neutral name for the counter.

With SPMC at S-EL2 OP-TEE will be virtualized and must us

Rename to barrier_read_counter_timer()

Renames barrier_read_cntpct() to barrier_read_counter_timer() to use a
neutral name for the counter.

With SPMC at S-EL2 OP-TEE will be virtualized and must use CNTVCT
instead of CNTPCT while the old physical OP-TEE must continue to use
CNTPCT.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: let struct tee_pager_area span multiple translation tables

Extends struct tee_pager_area to be able to span multiple translation
tables avoiding the need to split ranges into multiple a

core: pager: let struct tee_pager_area span multiple translation tables

Extends struct tee_pager_area to be able to span multiple translation
tables avoiding the need to split ranges into multiple areas in case a
range crosses a translation table boundary.

Tested-by: Jerome Forissier <jerome@forissier.org> (HiKey960)
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ls: enable CAAM DH

Enabled CAAM DH algorithm for all LS platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

core: imx: enable CAAM DH

Enable CAAM DH algorithm for all i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

drivers: caam: implement NXP CAAM Driver - DH

Add DH CAAM driver.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carrier

drivers: caam: implement NXP CAAM Driver - DH

Add DH CAAM driver.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: crypto: implement crypto driver - DH

Add a generic cryptographic DH driver interface connecting
TEE Crypto generic APIs to HW driver interface

Signed-off-by: Cedric Neveux <cedric.neveux@n

drivers: crypto: implement crypto driver - DH

Add a generic cryptographic DH driver interface connecting
TEE Crypto generic APIs to HW driver interface

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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Update CHANGELOG.md for 3.13.0

Update CHANGELOG for 3.13.0 and collect Tested-by tags.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6d

Update CHANGELOG.md for 3.13.0

Update CHANGELOG for 3.13.0 and collect Tested-by tags.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6dlsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6dlsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6qpsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6sllevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6ulevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6ullevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6ulzevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx7dsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx7ulpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx8mmevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx8mnevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx8mqevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx8qmmek)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx8qxpmek)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-ev1/dk2 gp pkcs11)
Tested-by: Igor Opaniuk <igor.opaniuk@foundries.io> (Poplar)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (imx-mx8mqevk)
Tested-by: Jerome Forissier <jerome@forissier.org> (HiKey GP PKCS#11)
Tested-by: Jerome Forissier <jerome@forissier.org> (HiKey960 GP PKCS#11)
Tested-by: Jerome Forissier <jerome@forissier.org> (QEMU GP PKCS#11)
Tested-by: Jerome Forissier <jerome@forissier.org> (QEMUv8 GP PKCS#11)
Tested-by: Joakim Bech <joakim.bech@linaro.org> (RPi3B)
Tested-by: Ricardo Salveti <ricardo@foundries.io> (ZynqMP)
Tested-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> (ccimx6ulsbcpro barebox upstream kernel)
Tested-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> (imx6qsabrelite barebox upstream kernel)
Tested-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> (RCAR M3)
Tested-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> (RCAR M3/virtualization)

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drivers: caam: fix CMAC update operation

Fix an issue in the CMAC do_update() operation that
would happen in the following conditions:
* a data temporay buffer full (16 bytes).
* an input message

drivers: caam: fix CMAC update operation

Fix an issue in the CMAC do_update() operation that
would happen in the following conditions:
* a data temporay buffer full (16 bytes).
* an input message of 16 bytes.

These conditions would set the data size to be processed by the CAAM
equals to zero. This would result on the loss of 16 bytes of the input
message and a wrong CMAC.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: fix input data size for CMAC do_update()

Fix a corner case where the CAAM would try to allocate an input
DMA object with a size of 0 bytes.

Signed-off-by: Cedric Neveux <cedric.neveu

drivers: caam: fix input data size for CMAC do_update()

Fix a corner case where the CAAM would try to allocate an input
DMA object with a size of 0 bytes.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: enable SCMI PTA interface

Enable SCMI PTA for REE to interface SCMI services in a threaded context.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wikla

plat-stm32mp1: enable SCMI PTA interface

Enable SCMI PTA for REE to interface SCMI services in a threaded context.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pta: scmi: new interface to REE SCMI agent

Adds a PTA interface to REE SCMI agents to get SCMI message communication
channel for processing in OP-TEE SCMI server.

Currently implement supports

core: pta: scmi: new interface to REE SCMI agent

Adds a PTA interface to REE SCMI agents to get SCMI message communication
channel for processing in OP-TEE SCMI server.

Currently implement supports for a SCMI server built with
CFG_SCMI_MSG_SMT=y. The implementation is made so that an alternate
SCMI server implementation can added.

Client gets SCMI channel capabilities with PTA_SCMI_CMD_CAPABILITIES.
Client gets a handle for an SCMI channel with command
PTA_SCMI_CMD_GET_CHANNEL_HANDLE.
Client pushes SCMI messages with command PTA_SCMI_CMD_PROCESS_SMT_CHANNEL
or PTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: scmi-msg: introduce scmi_smt_channel_handle()

New API function for scmi-msg drivers: sub channel ID to handle
conversion for consistency in SCMI PTA.

Signed-off-by: Etienne Carriere <etien

drivers: scmi-msg: introduce scmi_smt_channel_handle()

New API function for scmi-msg drivers: sub channel ID to handle
conversion for consistency in SCMI PTA.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat: rcar: use new register_ddr() macro

As register_dynamic_shm() is being retired - switch to the new macro.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Volodymyr Babchuk

plat: rcar: use new register_ddr() macro

As register_dynamic_shm() is being retired - switch to the new macro.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

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plat: rcar m3: Add support for 8GB version

Add support for M3 SOC with 8GB of RAM. In this case memory is organized in
two bank of 4GB. Renesas calls this variant 2x4g, so in OP-TEE we will have
fla

plat: rcar m3: Add support for 8GB version

Add support for M3 SOC with 8GB of RAM. In this case memory is organized in
two bank of 4GB. Renesas calls this variant 2x4g, so in OP-TEE we will have
flavor salvator_m3_2x4g.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

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libutee: include: fix typo in pta_invoke_tests.h

In PTA "invoke test", the AES performance test command takes
as argument key size value as bits instead of bytes.
Fix typo in comment.

Signed-off-by

libutee: include: fix typo in pta_invoke_tests.h

In PTA "invoke test", the AES performance test command takes
as argument key size value as bits instead of bytes.
Fix typo in comment.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: fix plat_scmi_get_channel() against invalid IDs

Fix plat_scmi_get_channel() to safely return NULL when channel ID
argument is invalid.

Signed-off-by: Etienne Carriere <etienne.carrie

plat-stm32mp1: fix plat_scmi_get_channel() against invalid IDs

Fix plat_scmi_get_channel() to safely return NULL when channel ID
argument is invalid.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: clock gating: atomic RCC registers access

Use io_{set|clr}bits32_stm32shregs() instead of io_{set|clr}bits32() for
SoC clock registers that must be locked while updated.

Signed-off-b

plat-stm32mp1: clock gating: atomic RCC registers access

Use io_{set|clr}bits32_stm32shregs() instead of io_{set|clr}bits32() for
SoC clock registers that must be locked while updated.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: disable BGET test

Disable BGET tests when pager is enabled since these can be very
very lengthy when pager page pool is small relatively to the tested
heap size.

Signed-off-by: Etien

plat-stm32mp1: disable BGET test

Disable BGET tests when pager is enabled since these can be very
very lengthy when pager page pool is small relatively to the tested
heap size.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: Add FFA_FEATURES handling for SPs

FFA_FEATURES is used to signal the supported FF-A features.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Acked-by: Etienne Carriere <etienne.carriere@linar

core: Add FFA_FEATURES handling for SPs

FFA_FEATURES is used to signal the supported FF-A features.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: Add FFA_VERSION handling for SPs

FFA_VERSION return the current support FF-A version

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>