core: lpae: add internal core_mmu_xlat_table_entry_pa2va()

core_mmu_xlat_table_entry_pa2va() allows to get the virtual address
of a table pointed by some other table entry.
Current it has a single u

core: lpae: add internal core_mmu_xlat_table_entry_pa2va()

core_mmu_xlat_table_entry_pa2va() allows to get the virtual address
of a table pointed by some other table entry.
Current it has a single use, but it will have few more usages later.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: lpae: search TAs VA base in the regions [1GB, 4GB[

In order to support 32-bit TAs we will have to find
a TAs VA base in the region of [1GB, 4GB[.
The 4GB limit wasn't enforced before this patc

core: lpae: search TAs VA base in the regions [1GB, 4GB[

In order to support 32-bit TAs we will have to find
a TAs VA base in the region of [1GB, 4GB[.
The 4GB limit wasn't enforced before this patch.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: lpae: extract 48 bits from table entry

Page table entry descriptor holds 48 bits of PA,
while only 40 were extracted.
This change is crucial to support more than 40 bits of addressing.

Signed

core: lpae: extract 48 bits from table entry

Page table entry descriptor holds 48 bits of PA,
while only 40 were extracted.
This change is crucial to support more than 40 bits of addressing.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: mmu: replace "1 << x" with "BIT64(x)"

"1" instead of "1ULL" caused issues with calculations
when address width is higher than 32 bits.
Uses BIT64() instead of explicit "1ULL".

Signed-off-by:

core: mmu: replace "1 << x" with "BIT64(x)"

"1" instead of "1ULL" caused issues with calculations
when address width is higher than 32 bits.
Uses BIT64() instead of explicit "1ULL".

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: lpae: use "base table" naming instead of "l1 table"

This is a preparation for supporting base table
which is not level 1 (i.e. support level 0).
Tries not to change anything functional, but
ra

core: lpae: use "base table" naming instead of "l1 table"

This is a preparation for supporting base table
which is not level 1 (i.e. support level 0).
Tries not to change anything functional, but
rather just a renaming.
"base table" terminology is referenced from TF-A
Renamed CORE_MMU_L1_TBL_OFFSET -> CORE_MMU_BASE_TABLE_OFFSET
Added CORE_MMU_BASE_TABLE_LEVEL instead of hard-coded "1"
Added CORE_MMU_BASE_TABLE_SHIFT instead of hard-coded "30"
Few new defines were copied from TF-A xlat_tables_def.h,
like the existing XLAT related defines.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: lpae: replace "3" with XLAT_TABLE_LEVEL_MAX

Just a cosmetic change for a better code readability.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@lina

core: lpae: replace "3" with XLAT_TABLE_LEVEL_MAX

Just a cosmetic change for a better code readability.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: lpae: fix 'idx' boundary check in core_mmu_entry_to_finer_grained()

Table entry index, 'idx', was checked for [0, tbl_info->num_entries],
while it should be [0, tbl_info->num_entries[.

Signed

core: lpae: fix 'idx' boundary check in core_mmu_entry_to_finer_grained()

Table entry index, 'idx', was checked for [0, tbl_info->num_entries],
while it should be [0, tbl_info->num_entries[.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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mk: fix test on gprof and shared libs configuration for TAs

Change test for when both CFG_TA_GPROF_SUPPORT and CFG_ULIBS_SHARED
are enabled to be more strict on switches expected value. This change

mk: fix test on gprof and shared libs configuration for TAs

Change test for when both CFG_TA_GPROF_SUPPORT and CFG_ULIBS_SHARED
are enabled to be more strict on switches expected value. This change
better handles cases where, for examples, CFG_GENERATE_DTB_OVERLAY
is not defined and is malformed CFG_EXTERNAL_DTB_OVERLAY=yy. In such
case we expect both switch to be disabled and build should not fail
with error message:
"CFG_EXTERNAL_DTB_OVERLAY and CFG_GENERATE_DTB_OVERLAY are exclusive"

Reported-by: Clement Leger <clement.leger@bootlin.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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build: ldelf and TAs can rely on CFLAGS32/CFLAGS64

Defines arch-bits-$(sm) for ldelf and intree TAs sub components
so that they can build using CFLAGS32 (or CFLAGS64) directives
possibly passed by t

build: ldelf and TAs can rely on CFLAGS32/CFLAGS64

Defines arch-bits-$(sm) for ldelf and intree TAs sub components
so that they can build using CFLAGS32 (or CFLAGS64) directives
possibly passed by the build environment.

Defines arch-bits-ta_arm32 (resp. 64) in TA devkit to leverage
CFLAGS32 (reps. CFLAGS64) directive passed by the build process. This
change is needed for external package willing to pass specific
directive to TA build sequence as toolchain's sysroot path.

Adds an inline comment describing $(sm) value in the in tree TAs build
instructions.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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core: Fix r7 clobbering in reset_primary

During reset_primary, r7 is used to keep the content of r2 register
given at OP-TEE start. However, r7 is clobbered during boot. This lead
to r2 being incorr

core: Fix r7 clobbering in reset_primary

During reset_primary, r7 is used to keep the content of r2 register
given at OP-TEE start. However, r7 is clobbered during boot. This lead
to r2 being incorrectly restored when returning to normal world. Use
r9 instead of r7 where needed to avoid clobbering it.

Fixes: 59ac3801b756 ("core: split boot_init_primary")
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: improve version string shown at boot time when not using Git

When OP-TEE is built outside of a Git repository, the implementation
version is shown as "Unknown" at boot time. For example:

I/T

core: improve version string shown at boot time when not using Git

When OP-TEE is built outside of a Git repository, the implementation
version is shown as "Unknown" at boot time. For example:

I/TC: OP-TEE version: Unknown (gcc version 10.2.1 ...

Improve this a bit by appending the major/minor revision of OP-TEE,
which is hardcoded in mk/config.mk and thus always available.

The above example becomes:

I/TC: OP-TEE version: Unknown_3.14 (gcc version 10.2.1 ...

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: remove duplicate definition of THREAD_CTX_SIZE

Following commit 1b302ac09816 ("core: enable FF-A with SPM Core at
S-EL1"), the THREAD_CTX_SIZE macro is now defined twice on arm64
(in $(

core: arm64: remove duplicate definition of THREAD_CTX_SIZE

Following commit 1b302ac09816 ("core: enable FF-A with SPM Core at
S-EL1"), the THREAD_CTX_SIZE macro is now defined twice on arm64
(in $(out-dir)/core/include/generated/asm-defines.h).

Kill the definition in the #ifdef ARM64 block and keep the common
one.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu: fix phys_to_virt() to check length

phys_to_virt() function without length parameter doesn`t
always have ability to find the correct mapping for
requested physical address. This is because

core_mmu: fix phys_to_virt() to check length

phys_to_virt() function without length parameter doesn`t
always have ability to find the correct mapping for
requested physical address. This is because physical
address can be mapped in the same time in different virtual
regions with different length. So the first found region
which contains the requested physical address possibly
doesn`t have enough mapped data. This is fixed by adding
the length parameter to phys_to_virt() function. Length
parameter can be set to 1 if caller knows that requested
(pa + len) doesn`t cross mapping granule boundary.

core_mmu_get_va() and io_pa_or_va() functions now are
take length parameter too as they based on phys_to_virt()
in case of MMU enabled.

Signed-off-by: Anton Rybakov <a.rybakov@omp.ru>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_DK2)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qpsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sllevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ullevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulzevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7dsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7ulpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mmevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mnevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mqevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qmmek)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qxpmek)

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core: arm: implement cpu_idle()

Implement cpu_idle() on arm and arm64, based on wfi(). With this patch,
a panicked CPU no longer burns cycles needlessly.

Signed-off-by: Jerome Forissier <jerome@for

core: arm: implement cpu_idle()

Implement cpu_idle() on arm and arm64, based on wfi(). With this patch,
a panicked CPU no longer burns cycles needlessly.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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arm64: add wfi()

arm32.h has a wfi() function but not arm64.h. Add it.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Et

arm64: add wfi()

arm32.h has a wfi() function but not arm64.h. Add it.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: panic: introduce cpu_idle() function

Adds a cpu_idle() weak function to panic.h/panic.c, which can later be
implemented in arch-specific code. The purpose is to avoid a busy loop
(which is the

core: panic: introduce cpu_idle() function

Adds a cpu_idle() weak function to panic.h/panic.c, which can later be
implemented in arch-specific code. The purpose is to avoid a busy loop
(which is the default implementation) when __do_panic() is done but
cannot return.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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ta: pkcs11: make heap size configurable

Add a configuration switch for the PKCS11 TA heap size defaulting
to 16kB as legacy.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-b

ta: pkcs11: make heap size configurable

Add a configuration switch for the PKCS11 TA heap size defaulting
to 16kB as legacy.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>

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ta: pkcs11: describe CFG_PKCS11_TA_TOKEN_COUNT

Add a default value and a description for PKCS11 TA config switch
CFG_PKCS11_TA_TOKEN_COUNT in ta/pkcs11/sub.mk.

Signed-off-by: Etienne Carriere <etie

ta: pkcs11: describe CFG_PKCS11_TA_TOKEN_COUNT

Add a default value and a description for PKCS11 TA config switch
CFG_PKCS11_TA_TOKEN_COUNT in ta/pkcs11/sub.mk.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>

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ta: pkcs11: move default config to ta sub.mk

Move PKCS#11 TA default configuration settings from mk/config.mk
to ta/pkcs11/sub.mk.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Revi

ta: pkcs11: move default config to ta sub.mk

Move PKCS#11 TA default configuration settings from mk/config.mk
to ta/pkcs11/sub.mk.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>

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ta: pkcs11: fix error code in asymmetric signature update sequence

Correct return code in asymmetric update sequence when digest of
the input data is updated on a multi-stage operation. Prior this
c

ta: pkcs11: fix error code in asymmetric signature update sequence

Correct return code in asymmetric update sequence when digest of
the input data is updated on a multi-stage operation. Prior this
change, the implementation returned CKR_GENERAL_ERROR instead of
CKR_OK because the expected success return value was loaded for
that stage.

Fixes: fb279d8b608e ("ta: pkcs11: Add support for elliptic curve signing & verification")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ruchika Gupta <ruchika.gupta@linaro.org>

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ta: pkcs11: Add operation state in session

Add more operation states to take care of scenarios like failure
of an incremental (update) operation if a one-shot/final operation
has been started.

Sign

ta: pkcs11: Add operation state in session

Add more operation states to take care of scenarios like failure
of an incremental (update) operation if a one-shot/final operation
has been started.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: rename TA_VASPACE to TS_VASPACE

The TA_VASPACE memory will be used by both TAs and SPs.
Rename it to TS_VASPACE so it is clearer that it can be used by both.

Signed-off-by: Jelle Sels <jelle.

core: rename TA_VASPACE to TS_VASPACE

The TA_VASPACE memory will be used by both TAs and SPs.
Rename it to TS_VASPACE so it is clearer that it can be used by both.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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MAINTAINERS: update reviewer of ls_gpio.c and ls_dspi.c

update reviewer of ls_gpio.c and ls_dspi.c

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissie

MAINTAINERS: update reviewer of ls_gpio.c and ls_dspi.c

update reviewer of ls_gpio.c and ls_dspi.c

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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MAINTAINERS: remove reviewer of ls_gpio.c and ls_dspi.c

manish.tomar@nxp.com is bouncing. His GitHub handle (@manishtomarnxp)
has had no activity since March 2020 and I found no way to reach him.
So

MAINTAINERS: remove reviewer of ls_gpio.c and ls_dspi.c

manish.tomar@nxp.com is bouncing. His GitHub handle (@manishtomarnxp)
has had no activity since March 2020 and I found no way to reach him.
So, remove him from MAINTAINERS.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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Squashed commit upgrading to mbedtls-2.27.0

Squash merging branch import/mbedtls-2.27.0

335b95f50f90 ("core: libmbedtls: add ctr_drbg.c to core sources")
9ad9df8b36e4 ("core: libtomcrypt: libmbed

Squashed commit upgrading to mbedtls-2.27.0

Squash merging branch import/mbedtls-2.27.0

335b95f50f90 ("core: libmbedtls: add ctr_drbg.c to core sources")
9ad9df8b36e4 ("core: libtomcrypt: libmbedtls: mbedtls_mpi_montred() now returns void")
ade0994c57b3 ("libmbedtls: add SM2 curve")
3041cf9726e2 ("libmbedtls: mbedtls_mpi_exp_mod(): optimize mempool usage")
a2e7a4cd262d ("libmbedtls: mbedtls_mpi_exp_mod(): reduce stack usage")
87efbd27f8e0 ("libmbedtls: mbedtls_mpi_exp_mod() initialize W")
e7c59b9b1d5f ("libmbedtls: fix no CRT issue")
d76bd278d9e2 ("libmbedtls: add interfaces in mbedtls for context memory operation")
e5b6c167f809 ("libmedtls: mpi_miller_rabin: increase count limit")
b81d896a903d ("libmbedtls: add mbedtls_mpi_init_mempool()")
3fbd8660c09d ("libmbedtls: make mbedtls_mpi_mont*() available")
2cc759c67e37 ("mbedtls: configure mbedtls to reach for config")
48bf81758c6e ("mbedtls: remove default include/mbedtls/config.h")
3602df84d7b3 ("Import mbedtls-2.27.0")

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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