libtomcrypt: disable -Wdeclaration-after-statement

Disables -Wdeclaration-after-statement when compiling the libtomcrypt
library in order to avoid that kind of warnings from upstream code.

Reviewed

libtomcrypt: disable -Wdeclaration-after-statement

Disables -Wdeclaration-after-statement when compiling the libtomcrypt
library in order to avoid that kind of warnings from upstream code.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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libmbedtls: disable -Wdeclaration-after-statement

Disabled -Wdeclaration-after-statement when compiling the mbedtls
library in order to avoid that kind of warnings from upstream code.

Reviewed-by:

libmbedtls: disable -Wdeclaration-after-statement

Disabled -Wdeclaration-after-statement when compiling the mbedtls
library in order to avoid that kind of warnings from upstream code.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-rzn1: Add Cortex-M3 start

The RZ/N1 platform contains a Cortex-M3 in addition to dual A7 cores.

Add CFG_BOOT_CM3 flat (default=y) to start the Cortex-M3 unit.

Signed-off-by: Ralph Siemsen <ra

plat-rzn1: Add Cortex-M3 start

The RZ/N1 platform contains a Cortex-M3 in addition to dual A7 cores.

Add CFG_BOOT_CM3 flat (default=y) to start the Cortex-M3 unit.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-rzn1: fix unmasked register writes

When writing all 32 bits of a register, there is no need for iomask_32
which performs a read-modify-write operation. Not only is it faster, but
certain hardwa

plat-rzn1: fix unmasked register writes

When writing all 32 bits of a register, there is no need for iomask_32
which performs a read-modify-write operation. Not only is it faster, but
certain hardware registers are write-only or have side effects on read.

Using iomask_32 was found to cause the following issues on RZ/N1:
- accessing the I2C EEPROM gives timeout errors on read
- serial console drops characters on input (eg. when pasting)
Switching to io_write32 for non-masked writes fixes the issues.

Fixes: f1cf4b79 ("Add support for Renesas RZ/N1 platform")
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: ltc: always define LTC_DER

tomcrypt_private.h uses ltc_asn1_list which is defined in tomcrypt_pk.h
only when LTC_DER is defined. Since tomcrypt_private.h is included
unconditionally in some fi

core: ltc: always define LTC_DER

tomcrypt_private.h uses ltc_asn1_list which is defined in tomcrypt_pk.h
only when LTC_DER is defined. Since tomcrypt_private.h is included
unconditionally in some files such as core/lib/libtomcrypt/tomcrypt.c
it needs to compile with no error. Therefore add -DLTC_DER.

Fixes the following error:

$ make CFG_CRYPTO=n CFG_REE_FS=n
...
CC out/arm-plat-vexpress/core/lib/libtomcrypt/tomcrypt.o
In file included from core/lib/libtomcrypt/tomcrypt.c:9:
core/lib/libtomcrypt/src/headers/tomcrypt_private.h:64:4: error: unknown type name ‘ltc_asn1_list’
64 | ltc_asn1_list *enc_data;
| ^~~~~~~~~~~~~
...

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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crypto: build aes-gcm*.c files only when both AES and GCM are enabled

crypto/aes-gcm*.c need building only when both CFG_CRYPTO_AES and
CFG_AES_GCM are enabled.

Signed-off-by: Jerome Forissier <jer

crypto: build aes-gcm*.c files only when both AES and GCM are enabled

crypto/aes-gcm*.c need building only when both CFG_CRYPTO_AES and
CFG_AES_GCM are enabled.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: dt_driver: debug trace if property not found

Adds a debug level trace message in dt_driver_device_from_node_idx_prop()
when unexpectedly not finding provider expected property in target node.

core: dt_driver: debug trace if property not found

Adds a debug level trace message in dt_driver_device_from_node_idx_prop()
when unexpectedly not finding provider expected property in target node.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-mediatek: set SHMEM base address after TZDRAM

In order to avoid hole between TZDRAM and SHMEM memory, the Non-secure
static shared memory physical base address is set by default just
after the

plat-mediatek: set SHMEM base address after TZDRAM

In order to avoid hole between TZDRAM and SHMEM memory, the Non-secure
static shared memory physical base address is set by default just
after the secure RAM (TZDRAM):
SHMEM_START = TZDRAM_START + TZDRAM_SIZE

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Julien Masson <jmasson@baylibre.com>

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plat-mediatek: define memory range

This patch registers the non-secure memory to support dynamic shm
registering.

The default RAM size has been set to 1 GiB and default RAM base
address set to 0x40

plat-mediatek: define memory range

This patch registers the non-secure memory to support dynamic shm
registering.

The default RAM size has been set to 1 GiB and default RAM base
address set to 0x40000000.
These values can be changed at compilation via CFG_DRAM_SIZE and
CFG_DRAM_BASE.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Julien Masson <jmasson@baylibre.com>

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config: add flag CFG_WARN_INSECURE

OP-TEE is a reference implementation for developers and device
manufacturers, which implies that there always is a need to fill in
missing pieces that cannot be do

config: add flag CFG_WARN_INSECURE

OP-TEE is a reference implementation for developers and device
manufacturers, which implies that there always is a need to fill in
missing pieces that cannot be done generically. The chipmakers often
have additional security configurations those needs to be configured
according to the chipmakers security guidelines and security
specifications.

To reduce the likelihood of running a vanilla configured OP-TEE we
introduce the flag CFG_WARN_INSECURE that will give warning messages in
the boot saying that the OP-TEE runs a configuration that might be
insecure. The intention is that the device manufacturer making the end
products should change the flag to "n" after implementing stubbed
functionality in OP-TEE and configuring their device according to the
chipmakers security guidelines and security specifications.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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crypto: se050: rename huk driver to die_id

The current HUK driver is not providing the platform Hardware Unique
Key but the DIE_ID.

This can logically be a source of confusion (and bugs) for many u

crypto: se050: rename huk driver to die_id

The current HUK driver is not providing the platform Hardware Unique
Key but the DIE_ID.

This can logically be a source of confusion (and bugs) for many users
not enabling this option.

This commit renames the huk.c file to die_id.c and replaces the
previous configuration option with another one that is semantically
accurate.

CFG_NXP_SE05X_HUK_DRV --> CFG_NXP_SE05X_DIEID_DRV

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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crypto: se050: Foundries Plug-and-Trust release 0.0.4

Notice that rebasing the Plug-and-Trust stack to pick up the NXP
Plug-and-Trust 3.03.00 release broke backwards compatibility with
previous OP-T

crypto: se050: Foundries Plug-and-Trust release 0.0.4

Notice that rebasing the Plug-and-Trust stack to pick up the NXP
Plug-and-Trust 3.03.00 release broke backwards compatibility with
previous OP-TEE versions. This is why this commit includes the
necessary update to adaptors/apdu.c

https://github.com/foundriesio/plug-and-trust/releases/tag/v0.0.3

Also the v.0.0.4 release includes support for APDU raw frame
transmission to the secure element (a new interface).
The OP-TEE PTA that makes use of that functionality shall be merged
after this commit.

https://github.com/foundriesio/plug-and-trust/releases/tag/v0.0.4

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-sam: enable clock framework support

Enable clock framework support to be able to build sama5d2 clock tree.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <cleme

plat-sam: enable clock framework support

Enable clock framework support to be able to build sama5d2 clock tree.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: add sub.mk for sam

Add sub.mk to for sam directory build.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

drivers: sam: add sama5d2 clock description

Add complete sama5d2 clock tree description which uses all the
previously described clocks.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acke

drivers: sam: add sama5d2 clock description

Add complete sama5d2 clock tree description which uses all the
previously described clocks.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: sam: add at91 clock interface

Add interface to all clocks that are needed to describe sama5d2 clock
tree.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <

drivers: sam: add at91 clock interface

Add interface to all clocks that are needed to describe sama5d2 clock
tree.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: sam: add pmc clock registering

Add all functions that will be used for PMC clocks registration.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.fe

drivers: sam: add pmc clock registering

Add all functions that will be used for PMC clocks registration.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: sam: add at91_system clock driver

Add driver for system clock.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Bori

drivers: sam: add at91_system clock driver

Add driver for system clock.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: sam: add at91_utmi clock driver

Add driver for UTMI clock.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Br

drivers: sam: add at91_utmi clock driver

Add driver for UTMI clock.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: sam: add at91_usb clock driver

Add driver for USB clocks.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Bre

drivers: sam: add at91_usb clock driver

Add driver for USB clocks.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: sam: add at91_sckc clock driver

Add driver for slow clock controller.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-b

drivers: sam: add at91_sckc clock driver

Add driver for slow clock controller.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: sam: add at91_programmable clock driver

Add driver for programmable clocks.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
A

drivers: sam: add at91_programmable clock driver

Add driver for programmable clocks.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: sam: add at91_plldiv clock driver

Add driver for PLLDIV.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brez

drivers: sam: add at91_plldiv clock driver

Add driver for PLLDIV.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: sam: add at91_pll clock driver

Add driver for PLL.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon

drivers: sam: add at91_pll clock driver

Add driver for PLL.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: sam: add at91_peripheral clock driver

Add driver for periheral clocks.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-

drivers: sam: add at91_peripheral clock driver

Add driver for periheral clocks.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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