MAINTAINERS: Updates related to GitHub IDs and email

- Update the MAINTAINERS file to reflect the removal of GitHub team
names. The GitHub team ID's weren't used much, hence we agreed to
delete

MAINTAINERS: Updates related to GitHub IDs and email

- Update the MAINTAINERS file to reflect the removal of GitHub team
names. The GitHub team ID's weren't used much, hence we agreed to
delete them.

- Add individual reviewers to platforms that previously just had a
GitHub team.

- Add missing GitHub ID's to some individuals names.

- Update email addresses to some individuals that have changed their
email address.

- Mark the HiSilicon D02 platform as Orphan.

- Mark the Spreadtrum SC9860 platform as Orphan.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Andrew Davis <afd@ti.com>

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Revert "ci: azure: remove build for CFG_FTRACE_SUPPORT=y and CFG_ULIBS_MCOUNT=y"

Now that the -Warray-bounds warnings are fixed with GCC 11.2 toolchain and
ftrace enabled, revert commit 8a5d06feb6b2

Revert "ci: azure: remove build for CFG_FTRACE_SUPPORT=y and CFG_ULIBS_MCOUNT=y"

Now that the -Warray-bounds warnings are fixed with GCC 11.2 toolchain and
ftrace enabled, revert commit 8a5d06feb6b2 ("ci: azure: remove build for
CFG_FTRACE_SUPPORT=y and CFG_ULIBS_MCOUNT=y").

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)

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ftrace: Refactor ftrace buffer dump implementation

Current implementation does a lot of tricky bits with ftrace buffer
pointer. It also leads to false positive -Warray-bounds warnings with
GCC 11.2

ftrace: Refactor ftrace buffer dump implementation

Current implementation does a lot of tricky bits with ftrace buffer
pointer. It also leads to false positive -Warray-bounds warnings with
GCC 11.2 toolchain as well. So refactor it to use array indexes instead.
Also, move hardcoded ftrace line sizes to macros instead for better
understanding.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)

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ci: azure: remove build for CFG_FTRACE_SUPPORT=y and CFG_ULIBS_MCOUNT=y

Removes build for CFG_FTRACE_SUPPORT=y, CFG_SYSCALL_FTRACE=y and
CFG_ULIBS_MCOUNT=y since they causes compile and link errors

ci: azure: remove build for CFG_FTRACE_SUPPORT=y and CFG_ULIBS_MCOUNT=y

Removes build for CFG_FTRACE_SUPPORT=y, CFG_SYSCALL_FTRACE=y and
CFG_ULIBS_MCOUNT=y since they causes compile and link errors for GCC
version 11.2.0.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: lpae: check return value of core_mmu_xlat_table_entry_pa2va()

Since core_mmu_xlat_table_entry_pa2va() can return a NULL pointer, check
its return value before the memcpy().

Fixes: 8bdbbf2f5 (

core: lpae: check return value of core_mmu_xlat_table_entry_pa2va()

Since core_mmu_xlat_table_entry_pa2va() can return a NULL pointer, check
its return value before the memcpy().

Fixes: 8bdbbf2f5 ("core: lpae: add internal core_mmu_entry_copy()")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: remove unnecessary header

Remove the following header:
* utee_defines.h

Fixes: f5a70e3e ("drivers: crypto: generic resources for crypto device driver - RSA")
Signed-off-by: Clement

drivers: crypto: remove unnecessary header

Remove the following header:
* utee_defines.h

Fixes: f5a70e3e ("drivers: crypto: generic resources for crypto device driver - RSA")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: remove unnecessary header

Remove the following header:
* utee_defines.h

Fixes: e43ab7a8 ("core: driver: generic resources for crypto cipher driver")
Signed-off-by: Clement Faure <

drivers: crypto: remove unnecessary header

Remove the following header:
* utee_defines.h

Fixes: e43ab7a8 ("core: driver: generic resources for crypto cipher driver")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: remove unnecessary header

Remove the following header:
* caam_utils_mem.h

Fixes: 2d7a8964 ("driver: implement CAAM driver")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acke

drivers: caam: remove unnecessary header

Remove the following header:
* caam_utils_mem.h

Fixes: 2d7a8964 ("driver: implement CAAM driver")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: fix potential memory leak

Free CAAM buffer pabufs before exiting the function in case of an error.

Fixes: 38923d487 ("drivers: caam: implement CAAM DMA Object")
Signed-off-by: Clemen

drivers: caam: fix potential memory leak

Free CAAM buffer pabufs before exiting the function in case of an error.

Fixes: 38923d487 ("drivers: caam: implement CAAM DMA Object")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: avoid arithmetic operation for pointer assignment

To parse the pointer array priv->sgtdata[], use this syntax array[idx]
instead of array + idx.
The new syntax is easier to read and l

drivers: caam: avoid arithmetic operation for pointer assignment

To parse the pointer array priv->sgtdata[], use this syntax array[idx]
instead of array + idx.
The new syntax is easier to read and less prone to errors.

Fixes: 38923d48 ("drivers: caam: implement CAAM DMA Object")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-aspeed: ast2600: control HACE into Secure World

1. Prohibit non-secure access to HACE controller
2. Grant TEE secure memory access to HACE.

Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Ac

plat-aspeed: ast2600: control HACE into Secure World

1. Prohibit non-secure access to HACE controller
2. Grant TEE secure memory access to HACE.

Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: crypto: aspeed: hace: fix digest incorrect problem

1. The processing status variable is not set to TEE_SUCCESS if
everything works fine.
2. DMA memory needs physically contiguous memory. Al

drivers: crypto: aspeed: hace: fix digest incorrect problem

1. The processing status variable is not set to TEE_SUCCESS if
everything works fine.
2. DMA memory needs physically contiguous memory. Allocate aligned
DMA memory and copy data from/to DMA memory to make sure consistency
of data.

Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: crypto: aspeed: hace: resolve build issues

Resolve various build and typo issues.

Fixes: commit e752c173aa0f ("crypto/aspeed: ast2600: Add HACE HW hash support")
Signed-off-by: Neal Liu <n

drivers: crypto: aspeed: hace: resolve build issues

Resolve various build and typo issues.

Fixes: commit e752c173aa0f ("crypto/aspeed: ast2600: Add HACE HW hash support")
Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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ci: azure: remove build for CFG_CORE_SANITIZE_UNDEFINED=y

OP-TEE and CFG_CORE_SANITIZE_UNDEFINED=y doesn't compile with newer
versions of GCC, anything from 8.x and onwards has problems. So disable

ci: azure: remove build for CFG_CORE_SANITIZE_UNDEFINED=y

OP-TEE and CFG_CORE_SANITIZE_UNDEFINED=y doesn't compile with newer
versions of GCC, anything from 8.x and onwards has problems. So disable
CI builds with CFG_CORE_SANITIZE_UNDEFINED=y until the problems have
been resolved.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: set CFG_TEE_CORE_LOG_LEVEL to 2 (info) by default

The default log level of the TEE core is 1 (error), which means it is
normally silent. Set it to 2 (info) so that the boot sequence can be
see

core: set CFG_TEE_CORE_LOG_LEVEL to 2 (info) by default

The default log level of the TEE core is 1 (error), which means it is
normally silent. Set it to 2 (info) so that the boot sequence can be
seen (OP-TEE version banner, CPUs detected etc.).

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: Fix compile warning in RPMB storage initialization

Fix the below warning when GCC 10.2.0 toolchain is used:

core/tee/tee_rpmb_fs.c:1137:3: warning: ‘dev_info’ may be used uninitialized in thi

core: Fix compile warning in RPMB storage initialization

Fix the below warning when GCC 10.2.0 toolchain is used:

core/tee/tee_rpmb_fs.c:1137:3: warning: ‘dev_info’ may be used uninitialized in this function [-Wmaybe-uninitialized]
memcpy(rpmb_ctx->cid, dev_info.cid, RPMB_EMMC_CID_SIZE);

Signed-off-by: Sadiq Hussain <sadiq.muchumarri@intel.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Update CHANGELOG for 3.17.0

Update CHANGELOG for 3.17.0 and collect Tested-by tags.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Joakim Bech <joakim.bech@linaro.org> (RP

Update CHANGELOG for 3.17.0

Update CHANGELOG for 3.17.0 and collect Tested-by tags.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Joakim Bech <joakim.bech@linaro.org> (RPi3B)
Tested-by: Joakim Bech <joakim.bech@linaro.org> (RPi3B-NFS)
Tested-by: Neal Liu <neal_liu@aspeedtech.com> (ast2600)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sllevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sxsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ullevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulzevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7dsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7ulpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mmevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mnevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mqevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qmmek)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qxpmek)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8dxlevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8ulpevk)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (hikey-hikey)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (imx-mx8mqevk)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Tested-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> (rcar-salvator_m3_2x4g / virt)
Tested-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> (rcar-salvator_m3_2x4g)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1012A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1028A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1088A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS2088A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1046A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1043A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS2160A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS2160A-QDS)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1, gp pkcs11)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (vexpress-qemu_virt, gp pkcs11 pager)

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ci: azure: build for rk3399

Add a build entry for Rockchip rk3399 (ROCK Pi 4 board).

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linar

ci: azure: build for rk3399

Add a build entry for Rockchip rk3399 (ROCK Pi 4 board).

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-rockchip: rk3399: define GICC_BASE

Commit 60801696667d ("plat: arm: refactor GIC initialization") has
introduced a build regression for Rockchip:

$ make -s PLATFORM=rockchip-rk3399
core/arch

plat-rockchip: rk3399: define GICC_BASE

Commit 60801696667d ("plat: arm: refactor GIC initialization") has
introduced a build regression for Rockchip:

$ make -s PLATFORM=rockchip-rk3399
core/arch/arm/plat-rockchip/main.c: In function ‘main_init_gic’:
core/arch/arm/plat-rockchip/main.c:29:29: error: ‘GICC_BASE’ undeclared (first use in this function); did you mean ‘GIC_BASE’?
29 | gic_init(&gic_data, GICC_BASE, GICD_BASE);
| ^~~~~~~~~
| GIC_BASE

Fix it by defining GICC_BASE unconditionally as most platforms do.
The value is taken from the DTS file from the Linux kernel [1].

Fixes: 60801696667d ("plat: arm: refactor GIC initialization")
Link: [1] https://github.com/torvalds/linux/blob/v5.17/arch/arm64/boot/dts/rockchip/rk3399.dtsi#L542
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat: arm: fix refactor GIC initialization

Commit 60801696667d ("plat: arm: refactor GIC initialization") converts
functions gic_init_base_addr() and gic_init() to take physical addresses
instead of

plat: arm: fix refactor GIC initialization

Commit 60801696667d ("plat: arm: refactor GIC initialization") converts
functions gic_init_base_addr() and gic_init() to take physical addresses
instead of virtual, but only converts half the platforms. This causes
boot failure on all the others.

Convert the rest here.

Fixes: 60801696667d ("plat: arm: refactor GIC initialization")
Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: wrap lines >80 characters; cite commit using commonly used format]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: caam: add JR interrupt only if CFG_CAAM_ITR=y

Adding the JR interrupt in the OPTEE CAAM driver, even if not used in
OPTEE, prevents the Linux CAAM driver from using the JR interrupt on
plat

drivers: caam: add JR interrupt only if CFG_CAAM_ITR=y

Adding the JR interrupt in the OPTEE CAAM driver, even if not used in
OPTEE, prevents the Linux CAAM driver from using the JR interrupt on
platforms sharing the same line of interruption for all job rings.

To dequeue job from the job ring, the Linux CAAM driver would pull the
number of jobs done from the output ring slot full register.

The fix is to add the JR interrupt only if CFG_CAAM_ITR=y. This
allows the Linux CAAM driver to dequeue jobs faster than polling from
a register.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: caam: fix function definition when CFG_CAAM_NO_ITR=y

There is a bug in the CAAM JR interruption enablement logic. When
CFG_CAAM_NO_ITR=y, the JR interruptions are used and when
CFG_CAAM_NO_

drivers: caam: fix function definition when CFG_CAAM_NO_ITR=y

There is a bug in the CAAM JR interruption enablement logic. When
CFG_CAAM_NO_ITR=y, the JR interruptions are used and when
CFG_CAAM_NO_ITR=n, the JR interruptions are not used.

Even with this wrong logic, the CAAM is still able to enqueue jobs.
When no JR interruptions are received, the CAAM will manually dequeue
jobs from the jobring by checking the number of jobs done in the output
ring slots full register.

CAAM JR interruptions are not mandatory for the CAAM to work properly
but it makes the dequeuing faster than polling the output ring slot full
register.

To avoid confusion, replace CFG_CAAM_NO_ITR with CFG_CAAM_ITR. The
CFG_CAAM_ITR is enabled by default and platforms not using the JR
interruptions would have this flag disabled instead.

Fixes: 3f45afc31 ("drivers: caam: disable the use of interrupts for some platforms")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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get_maintainer.py: add OP-TEE mailing list(s) to --release-to

The release annoucements should be sent to the general OP-TEE mailing
list(s), in addition to the maintainers and reviewers. Add the nee

get_maintainer.py: add OP-TEE mailing list(s) to --release-to

The release annoucements should be sent to the general OP-TEE mailing
list(s), in addition to the maintainers and reviewers. Add the needed
bits to extract this information.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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ta: pkcs11: PKCS11_CKM_AES_CBC_PAD is not supported

Remove PKCS11_CKM_AES_CBC_PAD from the list of the supported mechanism
as it is not implemented by the TA.

Fixes: https://github.com/OP-TEE/optee

ta: pkcs11: PKCS11_CKM_AES_CBC_PAD is not supported

Remove PKCS11_CKM_AES_CBC_PAD from the list of the supported mechanism
as it is not implemented by the TA.

Fixes: https://github.com/OP-TEE/optee_os/issues/5142
Acked-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: clk: Fix check for assigned-clock-rates index

Index should actually be strictly less than rate_len. Fix this which
might happen with the following description:

assigned-clock = <foo>, <bar

drivers: clk: Fix check for assigned-clock-rates index

Index should actually be strictly less than rate_len. Fix this which
might happen with the following description:

assigned-clock = <foo>, <bar>;
assigned-clock-parents = <foo_parent>, <bar_parent>;
assigned-clock-rates = <1000>;

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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