core: riscv.mk: disable unsupported configuration flags

Features which are not supported, or, specific to other
architectures are disabled.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.c

core: riscv.mk: disable unsupported configuration flags

Features which are not supported, or, specific to other
architectures are disabled.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

core: riscv: add plat-virt

Add Qemu Virt RISC-V platform.
Reference:
https://www.qemu.org/docs/master/system/riscv/virt.html

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: J

core: riscv: add plat-virt

Add Qemu Virt RISC-V platform.
Reference:
https://www.qemu.org/docs/master/system/riscv/virt.html

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-stm32mp1: restore BSEC SIP services on STM32MP15

U-Boot and Linux kernel use BSEC OP-TEE services on STM32MP15 but do
not yet integrate BSEC PTA drivers for OTP accesses and still rely on
OP-TE

plat-stm32mp1: restore BSEC SIP services on STM32MP15

U-Boot and Linux kernel use BSEC OP-TEE services on STM32MP15 but do
not yet integrate BSEC PTA drivers for OTP accesses and still rely on
OP-TEE BSEC SMC SiP service. Therefore restore the service for STM32MP15
platform flavors. The service will be default disabled once U-Boot and
Linux kernel are ready.

Fixes: eab9487631cc ("plat-stm32mp1: deprecate BSEC SIP services")
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-stm32mp1: fix visibility of stm32_bsec_shadow_register()

Makes stm32_bsec_shadow_register() function a visible driver API
function as it is needed when CFG_STM32_BSEC_SIP is enabled.
Fixed comm

plat-stm32mp1: fix visibility of stm32_bsec_shadow_register()

Makes stm32_bsec_shadow_register() function a visible driver API
function as it is needed when CFG_STM32_BSEC_SIP is enabled.
Fixed commit made it a local function which was wrong.

Fixes: a638030bce84 ("drivers: stm32_bsec: remove unused functions")
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

core: riscv: provide delay_arch.h

Implement timeout_init_us() and timeout_elapsed().

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@lin

core: riscv: provide delay_arch.h

Implement timeout_init_us() and timeout_elapsed().

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: kernel: delay: sort-out architecture-independant code from arch dir

This commit moves core/arch/arm/kernel/delay.c to core/kernel/delay.c.
Keeps architecture-dependant code in
core/arch/$ARCH/

core: kernel: delay: sort-out architecture-independant code from arch dir

This commit moves core/arch/arm/kernel/delay.c to core/kernel/delay.c.
Keeps architecture-dependant code in
core/arch/$ARCH/include/kernel/delay_arch.h and moves generic functions
to core/include/kernel/delay.h

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: riscv: add time source based on time registers

Implement a TEE time source based on CSR_TIME and CSR_HTIME for S-Mode
and CLINT MTIME register for M-Mode.
CFG_RISCV_TIME_SOURCE_RDTIME flag to

core: riscv: add time source based on time registers

Implement a TEE time source based on CSR_TIME and CSR_HTIME for S-Mode
and CLINT MTIME register for M-Mode.
CFG_RISCV_TIME_SOURCE_RDTIME flag to enable or not building the time
source. CFG_RISCV_MTIME_RATE defines the timer rate, default to 10MHz.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: move tee_time.c and tee_time_ree.c to core/kernel

tee_time.c and tee_time_ree.c are architecture-independant code therefore
move them from core/arch/arm/kernel to core/kernel.

Signed-off-by:

core: move tee_time.c and tee_time_ree.c to core/kernel

tee_time.c and tee_time_ree.c are architecture-independant code therefore
move them from core/arch/arm/kernel to core/kernel.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: riscv: provide <kernel/time.h>

Add read_time() function to get time based on CSR_TIME
and CSR_HTIME registers for S-Mode and CLINT MTIME register
for M-Mode.

Signed-off-by: Marouene Boubakri

core: riscv: provide <kernel/time.h>

Add read_time() function to get time based on CSR_TIME
and CSR_HTIME registers for S-Mode and CLINT MTIME register
for M-Mode.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: riscv: implement core local interruptor (clint) driver

An initial implementation of RISC-V CLINT driver with MTIMER
device to provide machine-level timer functionality.

Signed-off-by: Marouen

core: riscv: implement core local interruptor (clint) driver

An initial implementation of RISC-V CLINT driver with MTIMER
device to provide machine-level timer functionality.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: use SM3 crypto accelerated function

Uses the recently provided accelerated SM3 function in the SM3
implementation.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens

core: use SM3 crypto accelerated function

Uses the recently provided accelerated SM3 function in the SM3
implementation.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: arm64: SM3 using ARMv8.2-A cryptographic extensions

Import SM3 assembly code from the Linux kernel (Linaro contribution).
Enabled with CFG_CRYPTO_SM3_ARM64_CE=y, set by default if
CFG_CRYPTO_W

core: arm64: SM3 using ARMv8.2-A cryptographic extensions

Import SM3 assembly code from the Linux kernel (Linaro contribution).
Enabled with CFG_CRYPTO_SM3_ARM64_CE=y, set by default if
CFG_CRYPTO_WITH_CE82=y.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

ci: QEMUv8_check: run tests with v8.2 Cryptographic Extension enabled

Updates the line with regression tests with CFG_CRYPTO_WITH_CE=y to use
CFG_CRYPTO_WITH_CE82=y instead to include the v8.2 Crypt

ci: QEMUv8_check: run tests with v8.2 Cryptographic Extension enabled

Updates the line with regression tests with CFG_CRYPTO_WITH_CE=y to use
CFG_CRYPTO_WITH_CE82=y instead to include the v8.2 Cryptographic
Extension.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: mbedtls: use SHA-512 crypto accelerated routines

Uses the recently provided accelerated SHA-512 routine.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklan

core: mbedtls: use SHA-512 crypto accelerated routines

Uses the recently provided accelerated SHA-512 routine.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: ltc: use SHA-512 crypto accelerated function

Uses the recently provided accelerated SHA-512 function in LTC.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wikla

core: ltc: use SHA-512 crypto accelerated function

Uses the recently provided accelerated SHA-512 function in LTC.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: arm64: SHA-512 using ARMv8.2-A cryptographic extensions

Import SHA-512 assembly code from the Linux kernel (Linaro
contribution). Enabled with CFG_CRYPTO_SHA512_ARM64_CE=y, set by default
if C

core: arm64: SHA-512 using ARMv8.2-A cryptographic extensions

Import SHA-512 assembly code from the Linux kernel (Linaro
contribution). Enabled with CFG_CRYPTO_SHA512_ARM64_CE=y, set by default
if CFG_CRYPTO_WITH_CE82=y.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

libutee: riscv: modify the UTEE_SYSCALL assembly

Use li instead of mv in UTEE_SYSCALL, store the num_args
in the t1 register. This works on RV32 and RV64,
so change the compile control and rename th

libutee: riscv: modify the UTEE_SYSCALL assembly

Use li instead of mv in UTEE_SYSCALL, store the num_args
in the t1 register. This works on RV32 and RV64,
so change the compile control and rename the file.

Signed-off-by: liushiwei <liushiwei@eswincomputing.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: riscv: provide kern.ld.S

Provide script to allow linking OP-TEE core for RISC-V.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linar

core: riscv: provide kern.ld.S

Provide script to allow linking OP-TEE core for RISC-V.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: riscv: riscv.mk: add mm and tee subdirectories to build tree

Add mm and tee subdirectories to core-platform-subdirs.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by:

core: riscv: riscv.mk: add mm and tee subdirectories to build tree

Add mm and tee subdirectories to core-platform-subdirs.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: riscv: kernel: provide link.mk

Link and generate tee.(elf,bin,dmp,map,symb_sizes).

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@lin

core: riscv: kernel: provide link.mk

Link and generate tee.(elf,bin,dmp,map,symb_sizes).

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

crypto: se050: fix typo in information message

The SCP03 "built-in" keys were incorrectly being reported to the
console as a nonsensical "build-int".

Signed-off-by: Jorge Ramirez-Ortiz <jorge@found

crypto: se050: fix typo in information message

The SCP03 "built-in" keys were incorrectly being reported to the
console as a nonsensical "build-int".

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

crypto: se050: fix build warning

When the configured logging level does not output IMSG, the static
function get_scp03_ksrc_name() is not called.

This causes a function unused warning which might l

crypto: se050: fix build warning

When the configured logging level does not output IMSG, the static
function get_scp03_ksrc_name() is not called.

This causes a function unused warning which might lead to a build
error.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

ci: se05x crypto driver: enable fallback to softw-ops

Validates building the RSA/ECC fallback operations.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.

ci: se05x crypto driver: enable fallback to softw-ops

Validates building the RSA/ECC fallback operations.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

crypto: drivers: se050-f: ecc: can fallback to softw-ops

The SE050-F device can select to fallback to specific unsupported
operations.

This allows xtests to run to completion without errors.

Signe

crypto: drivers: se050-f: ecc: can fallback to softw-ops

The SE050-F device can select to fallback to specific unsupported
operations.

This allows xtests to run to completion without errors.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

crypto: drivers: se050-f: rsa: can fallback to softw-ops

The SE050-F device can select to fallback to specific unsupported
operations.

This allows xtests to run to completion without errors.

Signe

crypto: drivers: se050-f: rsa: can fallback to softw-ops

The SE050-F device can select to fallback to specific unsupported
operations.

This allows xtests to run to completion without errors.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...