dt-bindings: add stm32 TAMP support

Add device tree bindings for the TAMP hardware block stm32mpxx
platforms. These bindings permit the description of the configuration
of tamper events.

Signed-off

dt-bindings: add stm32 TAMP support

Add device tree bindings for the TAMP hardware block stm32mpxx
platforms. These bindings permit the description of the configuration
of tamper events.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rtc: add time stamping feature support

Support the time stamping features of the RTC. It is useful to generate
a timestamp whenever a particular event occurs.

Signed-off-by: Gatien C

drivers: stm32_rtc: add time stamping feature support

Support the time stamping features of the RTC. It is useful to generate
a timestamp whenever a particular event occurs.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: add stm32_gpio_get_bank_id() helper

Add stm32_gpio_get_bank_id() helper function to get the STM32
GPIO bank ID related to its GPIO chip

Signed-off-by: Gatien Chevallier <gatien

drivers: stm32_gpio: add stm32_gpio_get_bank_id() helper

Add stm32_gpio_get_bank_id() helper function to get the STM32
GPIO bank ID related to its GPIO chip

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: conf: default enable CFG_STM32_EXTI

Enable the driver stm32_exti on stm32mp2xx.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carr

plat-stm32mp2: conf: default enable CFG_STM32_EXTI

Enable the driver stm32_exti on stm32mp2xx.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: conf: default enable CFG_STM32_EXTI

Enable the driver stm32_exti on stm32mp1xx.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carr

plat-stm32mp1: conf: default enable CFG_STM32_EXTI

Enable the driver stm32_exti on stm32mp1xx.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add EXTI RIF configuration for the stm32mp257f-ev1 board

Add the RIF configuration for the stm32mp257f-ev1 board.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Et

dts: stm32: add EXTI RIF configuration for the stm32mp257f-ev1 board

Add the RIF configuration for the stm32mp257f-ev1 board.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add EXTI node in stm32mp251

Add the EXTI support for stm32mp25 SoC.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

dts: stm32: update EXTI node in stm32mp151

Update the EXTI support for stm32mp15 SoC.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st

dts: stm32: update EXTI node in stm32mp151

Update the EXTI support for stm32mp15 SoC.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add EXTI node in stm32mp131

Add the EXTI support for stm32mp13 SoC.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

drivers: add stm32 EXTI support

The stm32 EXTI peripheral is an interrupt controller that routes
the incoming interrupts to the GIC parent interrupt controller.
The EXTI can trigger the wake-up of t

drivers: add stm32 EXTI support

The stm32 EXTI peripheral is an interrupt controller that routes
the incoming interrupts to the GIC parent interrupt controller.
The EXTI can trigger the wake-up of the system on the incoming
interrupts.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: interrupt: add set_wake for power-management wake-on on interrupt

For interrupt controllers that can handle power-management wake-up
when receiving an interrupt, add the operation set_wake().

core: interrupt: add set_wake for power-management wake-on on interrupt

For interrupt controllers that can handle power-management wake-up
when receiving an interrupt, add the operation set_wake().

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: kernel: dt_driver: fix copy/paste comment

While adding DT_DRIVER_PINCTRL, an incorrect word was reported by
copy/paste from the existing comment for DT_DRIVER_RSTCTRL.

Drop the word 'reset' f

core: kernel: dt_driver: fix copy/paste comment

While adding DT_DRIVER_PINCTRL, an incorrect word was reported by
copy/paste from the existing comment for DT_DRIVER_RSTCTRL.

Drop the word 'reset' from the comment for DT_DRIVER_PINCTRL.

Fixes: b5aff6de7052 ("core: dt_driver: add support for DT_DRIVER_PINCTRL")
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: align RIMU documentation with STM32MP21

Update RIF_CIDSEL_P and RIF_CIDSEL_M defines to be align with STM32MP21.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-b

dt-bindings: align RIMU documentation with STM32MP21

Update RIF_CIDSEL_P and RIF_CIDSEL_M defines to be align with STM32MP21.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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ci: add STM32MP21 platforms build

Adds STM32MP215f-dk board build to the CI.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.c

ci: add STM32MP21 platforms build

Adds STM32MP215f-dk board build to the CI.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: add support of STM32MP21

Update RIMU table for SM32MP21.
RISAL is not supported on STM32MP21, so do not compile RISAL API in
RISFC for STM32MP21.

Signed-off-by: Thomas Bourgoi

drivers: stm32_rifsc: add support of STM32MP21

Update RIMU table for SM32MP21.
RISAL is not supported on STM32MP21, so do not compile RISAL API in
RISFC for STM32MP21.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: conf: support STM32MP21x SoC family

Add support for the STM32MP21x SoC family.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.che

plat-stm32mp2: conf: support STM32MP21x SoC family

Add support for the STM32MP21x SoC family.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add stm32mp215f-dk board

Add device tree files for stm32mp215f-dk.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st

dts: stm32: add stm32mp215f-dk board

Add device tree files for stm32mp215f-dk.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: st: introduce stm32mp21 SoCs family

STM32MP21 family is composed of 3 SoCs defined as following:

-STM32MP211: common part composed of 1*Cortex-A35, common peripherals
like SDMMC, UART, SPI, I2

dts: st: introduce stm32mp21 SoCs family

STM32MP21 family is composed of 3 SoCs defined as following:

-STM32MP211: common part composed of 1*Cortex-A35, common peripherals
like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ...

-STM32MP213: STM32MP211 + a second ETH, CAN-FD.

-STM32MP215: STM32MP213 + Display and CSI2.

A second diversity layer exists for security features/ A35 frequency:
-STM32MP21xY, "Y" gives information:
-Y = A means A35@1.2GHz + no CRYP IP and no secure boot.
-Y = C means A35@1.2GHz + cryp IP and secure boot.
-Y = D means A35@1.5GHz + no CRYP IP and no secure boot.
-Y = F means A35@1.5GHz + cryp IP and secure boot.

Available packages are:

STM32MP21xxAM: 14x14mm/TFBGA289 123 ios
STM32MP21xxAN: 11x11mm/VFBGA273 123 ios
STM32MP21xxAL: 10x10mm/VFBGA361 123 ios
STM32MP21xxAO: 8x8mm/VFBGA225 98 ios

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: add STM32MP21x shared bindings

Adds STM32MP21x SoC family bindings that share STM32MP25
RISAF bindings.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by:

dt-bindings: add STM32MP21x shared bindings

Adds STM32MP21x SoC family bindings that share STM32MP25
RISAF bindings.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: add STM32MP21 RIFSC bindings

Add STM32MP21 specific RIFSC bindings.

Co-developed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevalli

dt-bindings: add STM32MP21 RIFSC bindings

Add STM32MP21 specific RIFSC bindings.

Co-developed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ffa_console: register a DT_DRIVER_UART driver

This registers ffa_console driver as a DT_DRIVER_UART driver.

Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com>
Acked-by: Jerome Forissier <jer

drivers: ffa_console: register a DT_DRIVER_UART driver

This registers ffa_console driver as a DT_DRIVER_UART driver.

Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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ci: add AMD Versal Gen 2 platform

Add AMD Versal Gen 2 platform to CI Build.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Acked-by: Jens Wikl

ci: add AMD Versal Gen 2 platform

Add AMD Versal Gen 2 platform to CI Build.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

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drivers: amd: Add PS GPIO Support

Add PS GPIO Driver support for AMD Platforms.

The PS GPIO Controller is managed through the PS subsystem and
can operate in either the Secure World or the Non-Secu

drivers: amd: Add PS GPIO Support

Add PS GPIO Driver support for AMD Platforms.

The PS GPIO Controller is managed through the PS subsystem and
can operate in either the Secure World or the Non-Secure World.
The driver utilizes the Device Tree Blob (DTB) to determine whether the
PS GPIO Controller should be supported in the Secure World.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

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ci: further split QEMUv8 jobs

The two QEMUv8 jobs (1/2 and 2/2) take roughly 90 minutes to run while
the next longest job (QEMUv8, Xen) takes about 50 minutes. Split these
jobs further to reduce the

ci: further split QEMUv8 jobs

The two QEMUv8 jobs (1/2 and 2/2) take roughly 90 minutes to run while
the next longest job (QEMUv8, Xen) takes about 50 minutes. Split these
jobs further to reduce the overall duration of the CI pipeline.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@gmail.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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mk/config.mk: disable CFG_CALLOUT for CFG_CORE_SEL2_SPMC=y

With Hafnium at S-EL1 (CFG_CORE_SEL2_SPMC=y) the callout service isn't
initialized. To avoid unexpected aborts and errors, set CFG_CALLOUT=

mk/config.mk: disable CFG_CALLOUT for CFG_CORE_SEL2_SPMC=y

With Hafnium at S-EL1 (CFG_CORE_SEL2_SPMC=y) the callout service isn't
initialized. To avoid unexpected aborts and errors, set CFG_CALLOUT=n.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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