core: ffa: rename spmc_get_id() to get_my_id()

Renames spmc_get_id() to get_my_id() in order to avoid confusion with
the function FFA_SPM_ID_GET introduced with FF-A v1.1.

Reviewed-by: Jerome Foris

core: ffa: rename spmc_get_id() to get_my_id()

Renames spmc_get_id() to get_my_id() in order to avoid confusion with
the function FFA_SPM_ID_GET introduced with FF-A v1.1.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Balint Dobszay <balint.dobszay@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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ci: build CFG_CORE_SEL1_SPMC=y CFG_NS_VIRTUALIZATION=y

Add a build with both CFG_CORE_SEL1_SPMC=y and CFG_NS_VIRTUALIZATION=y.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off

ci: build CFG_CORE_SEL1_SPMC=y CFG_NS_VIRTUALIZATION=y

Add a build with both CFG_CORE_SEL1_SPMC=y and CFG_NS_VIRTUALIZATION=y.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: spmc: support virtualization with SPMC at S-EL1

Adds support for virtualization with OP-TEE as SPMC at S-EL1. This if
the FF-A counterpart of SMC based ABI with virtualization.

Reviewed-by: B

core: spmc: support virtualization with SPMC at S-EL1

Adds support for virtualization with OP-TEE as SPMC at S-EL1. This if
the FF-A counterpart of SMC based ABI with virtualization.

Reviewed-by: Balint Dobszay <balint.dobszay@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: register spmc_init() with boot_final()

In case of virtualization registers spmc_init() with boot_final()
instead of service_init() to have my_endpoint_id initialized as part of
boot initializa

core: register spmc_init() with boot_final()

In case of virtualization registers spmc_init() with boot_final()
instead of service_init() to have my_endpoint_id initialized as part of
boot initialization instead of delayed initialization when the OP-TEE
partition is created.

This guarantees that my_endpoint_id holds the correct value when the
first FF-A request is received.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add memory type MEM_AREA_NEX_NSEC_SHM

Adds the memory type MEM_AREA_NEX_NSEC_SHM used to map non-secure shared
memory in the nexus.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

core: add memory type MEM_AREA_NEX_NSEC_SHM

Adds the memory type MEM_AREA_NEX_NSEC_SHM used to map non-secure shared
memory in the nexus.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add virt_get_current_guest_id()

Adds the helper function virt_get_current_guest_id().

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander

core: add virt_get_current_guest_id()

Adds the helper function virt_get_current_guest_id().

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: spmc: support FF-A 1.1

Adds support for FF-A 1.1. Now OP-TEE will need to be able to work with
both version 1.0 and 1.1 depending on the other endpoint. The callee
supplies its implemented ver

core: spmc: support FF-A 1.1

Adds support for FF-A 1.1. Now OP-TEE will need to be able to work with
both version 1.0 and 1.1 depending on the other endpoint. The callee
supplies its implemented version and OP-TEE chooses the highest common
version and returns that. This is done per endpoint so some endpoint may
very well use version 1.0 while another uses version 1.1.

Two data structures, struct ffa_mem_transaction and struct
ffa_partition_info, are affected. Runtime conditionals are used to
select which version to use based on the negotiated FF-A version.

Reviewed-by: Balint Dobszay <balint.dobszay@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: spmc: improve checks in handle_mem_share()

For the two FF-A functions FFA_MEM_SHARE_64 and FFA_MEM_SHARE_32 update
the checks in handle_mem_share() for:
- 32-bit vs 64-bit calling convention,

core: spmc: improve checks in handle_mem_share()

For the two FF-A functions FFA_MEM_SHARE_64 and FFA_MEM_SHARE_32 update
the checks in handle_mem_share() for:
- 32-bit vs 64-bit calling convention, that is, when to mask of the
upper 32 bits.
- that the reported fragment length does not exceed the total length of
the memory transaction descriptor.

Reviewed-by: Balint Dobszay <balint.dobszay@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: use adr_l for __nex_bss_start and __nex_bss_end

Fixes the following linker errors when CFG_NS_VIRTUALIZATION is enabled:
.../entry_a64.o: in function `clear_bss':
.../entry_a64.

core: arm64: use adr_l for __nex_bss_start and __nex_bss_end

Fixes the following linker errors when CFG_NS_VIRTUALIZATION is enabled:
.../entry_a64.o: in function `clear_bss':
.../entry_a64.S:237:(.text._start+0x8c): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__nex_bss_start' defined in .bss.mempool_default section in all_objs.o
.../entry_a64.S:238:(.text._start+0x90): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__nex_bss_end' defined in .bss.mempool_default section in all_objs.o

Use the adr_l macro instead of adr to get the addresses for start and
end of .nex_bss.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: plat-virt: Override default platform ISA extensions

RV64 virtual platform on QEMU supports C(compressed), Zicsr, and
Zifencei extensions. To specify the ISA extensions into RISC-V
toolchain s

riscv: plat-virt: Override default platform ISA extensions

RV64 virtual platform on QEMU supports C(compressed), Zicsr, and
Zifencei extensions. To specify the ISA extensions into RISC-V
toolchain so that toolchain can generate the code correctly, these
ISA extensions should be encoded into "-march" flag. This patch
overrides the default ISA extensions which is defined in riscv.mk
to specify the extension that the platform really supports.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Add default variables for platform ISA, ABI and code model

In RISC-V, each platform may have different supported ISA extensions,
ABI, and code model. In this commit, we define the defau

core: riscv: Add default variables for platform ISA, ABI and code model

In RISC-V, each platform may have different supported ISA extensions,
ABI, and code model. In this commit, we define the default variables
of ISA extensions, ABI, and code model in RISC-V core Makefile. The
platform can further overrides the values in their plat-*/conf.mk.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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ta: pkcs11: invalidate handle of destroyed token objects

Marks as invalid any object handle that refers to the token object
that is being destroying so that any use of the related handle will
consid

ta: pkcs11: invalidate handle of destroyed token objects

Marks as invalid any object handle that refers to the token object
that is being destroying so that any use of the related handle will
consider the object handle as invalid.

Link: https://github.com/OP-TEE/optee_os/issues/6005
Reviewed-by: Valerii Chubar <valerii_chubar@epam.com>
Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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ta: pkcs11: invalidating handle in a database

Introduces a specific pointer value for handles that are no more valid
and API function handle_invalidate() to mark that a handle is no
more valid.

Rev

ta: pkcs11: invalidating handle in a database

Introduces a specific pointer value for handles that are no more valid
and API function handle_invalidate() to mark that a handle is no
more valid.

Reviewed-by: Valerii Chubar <valerii_chubar@epam.com>
Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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ta: pkcs11: factorize handle reference sanity test

Factorizes sanity validation of handle database and handle value
in pkcs11 TA handle functions

Reviewed-by: Valerii Chubar <valerii_chubar@epam.co

ta: pkcs11: factorize handle reference sanity test

Factorizes sanity validation of handle database and handle value
in pkcs11 TA handle functions

Reviewed-by: Valerii Chubar <valerii_chubar@epam.com>
Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: dt_driver_test: move source file to core/pta/test/

Moves dt_driver_test.c from core/kernel/ to core/pta/test/ where most
embedded tests implementation are located. This is legitimate as the
te

core: dt_driver_test: move source file to core/pta/test/

Moves dt_driver_test.c from core/kernel/ to core/pta/test/ where most
embedded tests implementation are located. This is legitimate as the
test results are retrieved from the Invoke PTA interface, even if the
test is not effectively run from an invocation command of that PTA.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: dt_driver_test: fix test failure status

Before this change, failing clock/reset/gpios tests do print a
"not run" status message because related status dt_test_state.probe_xxx
remains to DEFAUL

core: dt_driver_test: fix test failure status

Before this change, failing clock/reset/gpios tests do print a
"not run" status message because related status dt_test_state.probe_xxx
remains to DEFAULT value and are never set to FAILED. Fix this and
move each test to a specific local function to ease error cases
management using 'goto' instructions.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: dt_driver_test: clarify "not run" status message

Changes trace message from "not passed" to "not run" when a test
is not run.

Suggested-by: Jerome Forissier <jerome.forissier@linaro.org>
Acke

core: dt_driver_test: clarify "not run" status message

Changes trace message from "not passed" to "not run" when a test
is not run.

Suggested-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: interrupt: rename itr_init()

Renames itr_init() to interrupt_main_init() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by: Jens Wiklander <je

core: interrupt: rename itr_init()

Renames itr_init() to interrupt_main_init() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: interrupt: rename itr_core_handler()

Renames itr_core_handler() to interrupt_main_handler() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by:

core: interrupt: rename itr_core_handler()

Renames itr_core_handler() to interrupt_main_handler() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: gic: factorize call to gic_init() or gic_init_base_addr()

Platforms call either gic_init() or gic_init_base_addr() depending
on whether CFG_WITH_ARM_TRUSTED_FW is defined or not. This chang

drivers: gic: factorize call to gic_init() or gic_init_base_addr()

Platforms call either gic_init() or gic_init_base_addr() depending
on whether CFG_WITH_ARM_TRUSTED_FW is defined or not. This change
factorize this logic from gic_init() implementation and makes
gic_init_base_addr() local to gic.c.

For that purpose functions gic_init_base_address() and gic_dt_get_irq()
are moved inside gic.c source file.
source file.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: define main interrupt controller data from its driver

All but one platforms define CPU core interrupt controller from their
platform main.c source file next to its main interrupt handler.
This

core: define main interrupt controller data from its driver

All but one platforms define CPU core interrupt controller from their
platform main.c source file next to its main interrupt handler.
This change factorize these implementation by moving the definition
of the controller data instance straight in the controller driver
source file. This change makes each controller driver to implement
straight itr_core_handler() function, preventing a extra branch on
interrupt execution. Interrupt controller driver initialization
function now straight calls itr_core_init().

This changes treats case when CFG_CORE_WORKAROUND_ARM_NMFI is enable
to not conflict with core/arch/arm/kernel/thread.c that already
overrides itr_core_handler() weak implementation.

With this change, the main controller initialization function
(gic_init(), gic_init_base_addr(), gic_cpu_init() and hfic_init())
no more gets the controller data as input argument.

As a consequence, definition of struct hfic_data and struct gic_data
moves from their respective driver header file to the respective
driver source file.

As a consequence, gic_dump() no more requires an argument.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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MAINTAINERS: update etienne's e-mail address

Updates etienne-lms e-mail address.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed

MAINTAINERS: update etienne's e-mail address

Updates etienne-lms e-mail address.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: enable pinctrl and atmel_pio driver for wlsom1 board

The board will need these options to apply I2C pin muxing in order to
communicate with the PMIC.

Signed-off-by: Clément Léger <clement

plat-sam: enable pinctrl and atmel_pio driver for wlsom1 board

The board will need these options to apply I2C pin muxing in order to
communicate with the PMIC.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

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dts: at91: set PIO controller as secure

Set the PIO pinctrl as secure to ensure pin configurations are not
modifiable by non secure world.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
A

dts: at91: set PIO controller as secure

Set the PIO pinctrl as secure to ensure pin configurations are not
modifiable by non secure world.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

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drivers: pinctrl: atmel_pio: add pio controller for sama5d2

Add pinctrl driver for sama5d2 PIO controller. This driver adds support
to apply pin muxing configurations that are handled by the PIO
con

drivers: pinctrl: atmel_pio: add pio controller for sama5d2

Add pinctrl driver for sama5d2 PIO controller. This driver adds support
to apply pin muxing configurations that are handled by the PIO
controller.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

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