libutee: increase MPI_MEMPOOL_SIZE to 14Kb

With the Widevine v17/v18 OPKs using their new Provisioning 4.0
technique, this pool size needs to be increased to 14Kb from 12Kb.

The sequence that is be

libutee: increase MPI_MEMPOOL_SIZE to 14Kb

With the Widevine v17/v18 OPKs using their new Provisioning 4.0
technique, this pool size needs to be increased to 14Kb from 12Kb.

The sequence that is being executed that requires this is as follows:
1. TEE_GenerateKey(key_handle, 2048, NULL, 0)
2. TEE_GetObjectBufferAttribute(key, TEE_ATTR_RSA_MODULUS,
modulus_data, &modulus_len),
same for TEE_ATTR_RSA_PUBLIC_EXPONENT and
TEE_ATTR_RSA_PRIVATE_EXPONENT.
3. mbedtls_rsa_complete() on a pk object created from the extracted
modulus, public exp and private exp.

Signed-off-by: Jeffrey Kardatzke <jkardatzke@google.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: remove keep pager directive on core_init_mmu_regs()

Function core_init_mmu_regs() does not need to be unpaged, it is needed
at core initialization before MMU is setup. Remove DECLARE_KEEP_PAGE

core: remove keep pager directive on core_init_mmu_regs()

Function core_init_mmu_regs() does not need to be unpaged, it is needed
at core initialization before MMU is setup. Remove DECLARE_KEEP_PAGER()
directive (as done in core_mmu_lpae.c) as core_init_mmu_map() already
brings core_init_mmu_regs() in the init sections.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: conf: support 32bit MMU

Updates CFG_TEE_RAM_VA_SIZE default value and MAX_XLAT_TABLES when
32bit-MMU mapping is used instead of LPAE and default disable LPAE
for STM32MP15 with pager.

plat-stm32mp1: conf: support 32bit MMU

Updates CFG_TEE_RAM_VA_SIZE default value and MAX_XLAT_TABLES when
32bit-MMU mapping is used instead of LPAE and default disable LPAE
for STM32MP15 with pager. This setup optimizes pager resident memory
by about 4kB (1 physical page) in current platform default configuration.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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clk: stm32mp15: embed clock names only in debug mode

Don't embed clock names when not in debug mode, even when log level
is DEBUG_LEVEL. This saves few bytes of SYSRAM for the pager.

Acked-by: Gati

clk: stm32mp15: embed clock names only in debug mode

Don't embed clock names when not in debug mode, even when log level
is DEBUG_LEVEL. This saves few bytes of SYSRAM for the pager.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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libutee: add TEE_ALG_ECDSA_SHA* to TEE_ALG_GET_DIGEST_SIZE()

The TEE_ALG_GET_DIGEST_SIZE() macro lacks the ECDSA algorithms. Add
them.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

libutee: add TEE_ALG_ECDSA_SHA* to TEE_ALG_GET_DIGEST_SIZE()

The TEE_ALG_GET_DIGEST_SIZE() macro lacks the ECDSA algorithms. Add
them.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mbedtls: ecc_get_keysize(): do not check algorithm against curve

Since commit fe2fd3ff46c0 ("GP131: Add TEE_ALG_ECDH_DERIVE_SHARED_SECRET
and TEE_ALG_ECDSA_SHA*"), the algorithm and curve valu

core: mbedtls: ecc_get_keysize(): do not check algorithm against curve

Since commit fe2fd3ff46c0 ("GP131: Add TEE_ALG_ECDH_DERIVE_SHARED_SECRET
and TEE_ALG_ECDSA_SHA*"), the algorithm and curve values are not tied
as closely as before. The GP TEE Internal Core API specification v1.3.1
mentions "ECDSA algorithm identifiers should be tied to the size of the
digest, not the key. The key size information is provided with the key
material." (Table B-2). In other words, a number of algorithm values
are valid for use with any given ECC curve. Therefore remove the
algorithm checks in ecc_get_keysize(). This function is not the proper
place anyways.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: versal: do not use deprecated algorithm macros

The TEE_ALG_ECDSA_P384 and TEE_ALG_ECDSA_P521 constants are deprecated
since commit fe2fd3ff46c0 ("GP131: Add TEE_ALG_ECDH_DERIVE_SHAR

drivers: crypto: versal: do not use deprecated algorithm macros

The TEE_ALG_ECDSA_P384 and TEE_ALG_ECDSA_P521 constants are deprecated
since commit fe2fd3ff46c0 ("GP131: Add TEE_ALG_ECDH_DERIVE_SHARED_SECRET
and TEE_ALG_ECDSA_SHA*"). Therefore use TEE_ALG_ECDSA_SHA384 or
TEE_ALG_ECDSA_SHA512 instead (no functional change since the
aforementioned commit made them equal).

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: se050: do not use deprecated algorithm macros

The TEE_ALG_ECD{H,SA}_P* constants are deprecated since
commit fe2fd3ff46c0 ("GP131: Add TEE_ALG_ECDH_DERIVE_SHARED_SECRET and
TEE_ALG_

drivers: crypto: se050: do not use deprecated algorithm macros

The TEE_ALG_ECD{H,SA}_P* constants are deprecated since
commit fe2fd3ff46c0 ("GP131: Add TEE_ALG_ECDH_DERIVE_SHARED_SECRET and
TEE_ALG_ECDSA_SHA*"). Therefore use TEE_ALG_ECDSA_SHA* or
TEE_ALG_ECDH_DERIVE_SHARED_SECRET instead (no functional change since
the aforementioned commit made them equal)

Additional checks tying the curve to the algorithm do not apply anymore
since the key size (defined by the curve constant: TEE_ECC_CURVE_*) is
not the same as the hash size anymore (defined by the algorithm:
TEE_ALG_ECDSA_SHA* or TEE_ALG_ECDH_DERIVE_SHARED_SECRET).

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix out-of-bounds access of dump_ctx

Problem: in the case of no UTA running, the buffer of dump_ctx will
be allocated with 0 size and passed to init_dump_ctx(). That causes
buffer overrunning.

core: fix out-of-bounds access of dump_ctx

Problem: in the case of no UTA running, the buffer of dump_ctx will
be allocated with 0 size and passed to init_dump_ctx(). That causes
buffer overrunning.

Solution: Check buffer size before allocate the buffer. If it's 0,
return TEE_ERROR_ITEM_NOT_FOUND.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Weizhao Jiang <weizhaoj@amazon.com>
Signed-off-by: Weizhao Jiang <weizhaoj@amazon.com>

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drivers: atmel_tcb: Use matrix_dt_get_id() to correctly retrieve the id

Use matrix_dt_get_id() instead of manual address parsing to determine
which matrix ID is to be used. Previously it was plain w

drivers: atmel_tcb: Use matrix_dt_get_id() to correctly retrieve the id

Use matrix_dt_get_id() instead of manual address parsing to determine
which matrix ID is to be used. Previously it was plain wrong since it
compared a virtual address to a physical one and thus compute a wrong
value.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-sam: matrix: add matrix_dt_get_id() to parse matrix id from dt

Rather than using hardcoded values for matrix identifier in drivers
themselves, (which might change in future hardware SoC), add
m

plat-sam: matrix: add matrix_dt_get_id() to parse matrix id from dt

Rather than using hardcoded values for matrix identifier in drivers
themselves, (which might change in future hardware SoC), add
matrix_dt_get_id() function which allows to retrieve the ID based on a
devite-tree node reg property. This property contains the address of the
peripheral and thus can be used to match the address with an identifier.
This is also useful for peripheral which have multiple instances and thus
id is not the same for all of them.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: pta: imx: add manufacturing protection

Add the i.MX PTA to expose CAAM manufacturing protection features:
* Get manufacturing protection public key.
* Get manufacturing protection message.

core: pta: imx: add manufacturing protection

Add the i.MX PTA to expose CAAM manufacturing protection features:
* Get manufacturing protection public key.
* Get manufacturing protection message.
* Message signature with manufacturing protection private key.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: caam: add manufacturing protection feature

The CAAM features a "manufacturing protection" functionality.
It is a authentication process used to authenticate the chip to
the OEM's server. Th

drivers: caam: add manufacturing protection feature

The CAAM features a "manufacturing protection" functionality.
It is a authentication process used to authenticate the chip to
the OEM's server. The authentication process can ensure the chip:
* is a genuine NXP part
* is a correct part type
* has been properly fused
* is running a authenticated software
* runs in secure/trusted mode.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: crypto: add support MD5 hashes in RSA sign/verify/cipher

Introduce support of using MD5 hashes in RSA sign/verify/cipher
operations, which is required by AOSP Keymaster.

This is verified in

core: crypto: add support MD5 hashes in RSA sign/verify/cipher

Introduce support of using MD5 hashes in RSA sign/verify/cipher
operations, which is required by AOSP Keymaster.

This is verified in VerificationOperationsTest.RsaSuccess VTS Test [1],
which checks usage of such digests: NONE, MD5, SHA1, SHA_2_224, SHA_2_256,
SHA_2_384, SHA_2_512.

This patch has been inspired by commit[2]:

Link: [1] https://android.googlesource.com/platform/hardware/interfaces/+/master/keymaster/3.0/vts/functional/keymaster_hidl_hal_test.cpp
Link: [2] https://github.com/OP-TEE/optee_os/commit/199d0b7310d1705661a106358f1f0b46e4c5c587 ("core: crypto: add support MD5 hashes in RSA sign/verify")
Signed-off-by: Julien Masson <jmasson@baylibre.com>
Signed-off-by: Safae Ouajih <souajih@baylibre.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: drivers: zynqmp_csu_puf.c: increase regen time to 6ms

With further evaluation of the ZU+ PUF, we have determined that it is
possible for the PUF regeneration time to exceed 3ms. For this reas

core: drivers: zynqmp_csu_puf.c: increase regen time to 6ms

With further evaluation of the ZU+ PUF, we have determined that it is
possible for the PUF regeneration time to exceed 3ms. For this reason,
the 2023.1 version of the Xilinx xilskey library will bump the wait time
for PUF regeneration to 6ms. This patch brings optee in line with this
change.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

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core: crypto: change supported HMAC key size ranges

Change supported HMAC key size range from 64 to 1024 when
CFG_HMAC_64_1024_RANGE config is enabled, This is required
to successfully pass AOSP Key

core: crypto: change supported HMAC key size ranges

Change supported HMAC key size range from 64 to 1024 when
CFG_HMAC_64_1024_RANGE config is enabled, This is required
to successfully pass AOSP Keymaster VTS tests.

From TEE Internal Core API specificaion:
"Table 5-9, support for other sizes or algorithms
is implementation-defined."

Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Signed-off-by: Safae Ouajih <souajih@baylibre.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-totalcompute: remap console logs

Remapping console logs from soc uart1 (s0 termial)
to css secure (uart1_ap terminal)

Signed-off-by: Annam Sai Manisha <annam.saimanisha@arm.com>
Acked-by: Jens

plat-totalcompute: remap console logs

Remapping console logs from soc uart1 (s0 termial)
to css secure (uart1_ap terminal)

Signed-off-by: Annam Sai Manisha <annam.saimanisha@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: add SM2 ECC encrypt and decrypt

Adds operation handlers for decryption with ECC public keys and
encryption with ECC private keys and implements SM2 curves asymmetric
ciphering.

Sig

drivers: crypto: add SM2 ECC encrypt and decrypt

Adds operation handlers for decryption with ECC public keys and
encryption with ECC private keys and implements SM2 curves asymmetric
ciphering.

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

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drivers: crypto: add SM2 curve in crypto API

Add SM2 curve in function get_ecc_key_size_bytes().

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.or

drivers: crypto: add SM2 curve in crypto API

Add SM2 curve in function get_ecc_key_size_bytes().

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

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ci: qemuv8: build with maximum log level

Build qemuv8 platform with log core and TA levels set to
the maximum.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <je

ci: qemuv8: build with maximum log level

Build qemuv8 platform with log core and TA levels set to
the maximum.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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ta: pkcs11: fix trace compilation warning

Fix the following compilation issue:
$ make PLATFORM=imx-mx8mmevk CFG_TEE_TA_LOG_LEVEL=4 CFG_PKCS11_TA=y

In file included from out/arm-plat-imx/export-ta_a

ta: pkcs11: fix trace compilation warning

Fix the following compilation issue:
$ make PLATFORM=imx-mx8mmevk CFG_TEE_TA_LOG_LEVEL=4 CFG_PKCS11_TA=y

In file included from out/arm-plat-imx/export-ta_arm64/include/assert.h:9,
from ta/pkcs11/src/entry.c:6:
ta/pkcs11/src/entry.c: In function ‘TA_InvokeCommandEntryPoint’:
ta/pkcs11/src/entry.c:143:14: warning: format ‘%u’ expects argument of type ‘unsigned int’, but argument 7 has type ‘size_t’ {aka ‘long unsigned int’} [-Wformat=]
143 | DMSG("%s p#0 %"PRIu32"@%p, p#1 %s %"PRIu32"@%p, p#2 %s %"PRIu32"@%p",
| ^~~~~~~~~~
144 | id2str_ta_cmd(cmd),
145 | params[0].memref.size, params[0].memref.buffer,
| ~~~~~~~~~~~~~~~~~~~~~
| |
| size_t {aka long unsigned int}
out/arm-plat-imx/export-ta_arm64/include/trace.h:41:22: note: in definition of macro ‘trace_printf_helper’
41 | __VA_ARGS__)
| ^~~~~~~~~~~
ta/pkcs11/src/entry.c:143:9: note: in expansion of macro ‘DMSG’
143 | DMSG("%s p#0 %"PRIu32"@%p, p#1 %s %"PRIu32"@%p, p#2 %s %"PRIu32"@%p",
| ^~~~
ta/pkcs11/src/entry.c:143:23: note: format string is defined here
143 | DMSG("%s p#0 %"PRIu32"@%p, p#1 %s %"PRIu32"@%p, p#2 %s %"PRIu32"@%p",
| ~^
| |
| unsigned int
| %lu
ta/pkcs11/src/entry.c:143:14: warning: format ‘%u’ expects argument of type ‘unsigned int’, but argument 10 has type ‘size_t’ {aka ‘long unsigned int’} [-Wformat=]
143 | DMSG("%s p#0 %"PRIu32"@%p, p#1 %s %"PRIu32"@%p, p#2 %s %"PRIu32"@%p",
| ^~~~~~~~~~
......
148 | param_is_memref(ptypes, 1) ? params[1].memref.size : 0,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| size_t {aka long unsigned int}
out/arm-plat-imx/export-ta_arm64/include/trace.h:41:22: note: in definition of macro ‘trace_printf_helper’
41 | __VA_ARGS__)
| ^~~~~~~~~~~
ta/pkcs11/src/entry.c:143:9: note: in expansion of macro ‘DMSG’
143 | DMSG("%s p#0 %"PRIu32"@%p, p#1 %s %"PRIu32"@%p, p#2 %s %"PRIu32"@%p",
| ^~~~
ta/pkcs11/src/entry.c:143:14: warning: format ‘%u’ expects argument of type ‘unsigned int’, but argument 13 has type ‘size_t’ {aka ‘long unsigned int’} [-Wformat=]
143 | DMSG("%s p#0 %"PRIu32"@%p, p#1 %s %"PRIu32"@%p, p#2 %s %"PRIu32"@%p",
| ^~~~~~~~~~
......
152 | param_is_memref(ptypes, 2) ? params[2].memref.size : 0,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| size_t {aka long unsigned int}
out/arm-plat-imx/export-ta_arm64/include/trace.h:41:22: note: in definition of macro ‘trace_printf_helper’
41 | __VA_ARGS__)
| ^~~~~~~~~~~
ta/pkcs11/src/entry.c:143:9: note: in expansion of macro ‘DMSG’
143 | DMSG("%s p#0 %"PRIu32"@%p, p#1 %s %"PRIu32"@%p, p#2 %s %"PRIu32"@%p",
| ^~~~

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: caam: enable the CAAM clock when submitting a new job

Make sure the CAAM clock is running before writing to CAAM registers
when submitting a new CAAM job.
Otherwise, it would generate an OP

drivers: caam: enable the CAAM clock when submitting a new job

Make sure the CAAM clock is running before writing to CAAM registers
when submitting a new CAAM job.
Otherwise, it would generate an OPTEE data-abort.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: caam: add missing header file

Fix the following warning:

In file included from core/drivers/crypto/caam/hal/imx_8m/hal_cfg.c:8:
core/drivers/crypto/caam/hal/imx_8m/../../include/caam_hal_j

drivers: caam: add missing header file

Fix the following warning:

In file included from core/drivers/crypto/caam/hal/imx_8m/hal_cfg.c:8:
core/drivers/crypto/caam/hal/imx_8m/../../include/caam_hal_jr.h:22:16: warning: ‘enum caam_jr_owner’ declared inside parameter list will not be visible outside of this definition or declaration
22 | enum caam_jr_owner owner);
| ^~~~~~~~~~~~~

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: imx: use register_ddr() to register dynamic shared memory

Use register_ddr() to register all the DDR memory. Secure memory chunks
are automatically carved-out of the defined DDR memory ranges.

core: imx: use register_ddr() to register dynamic shared memory

Use register_ddr() to register all the DDR memory. Secure memory chunks
are automatically carved-out of the defined DDR memory ranges.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: clk: sam: remove hard coded USB clock setup

Now that USB clock is exposed and usable from the device-tree, we can rely
on the "assigned-clock" properties that have been added in the
device-

drivers: clk: sam: remove hard coded USB clock setup

Now that USB clock is exposed and usable from the device-tree, we can rely
on the "assigned-clock" properties that have been added in the
device-tree.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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