History log of /optee_os/ (Results 2276 – 2300 of 8578)
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ed33eb2e05-Feb-2023 Etienne Carriere <etienne.carriere@linaro.org>

core: dt_driver: define interrupt controller drivers identifier

Defines identifier DT_DRIVER_INTERRUPT in dt_driver_type enumerated type
for interrupt controller drivers.

Acked-by: Jens Wiklander <

core: dt_driver: define interrupt controller drivers identifier

Defines identifier DT_DRIVER_INTERRUPT in dt_driver_type enumerated type
for interrupt controller drivers.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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be53ee7b06-Jun-2023 Etienne Carriere <etienne.carriere@foss.st.com>

plat-stm32mp1: fix default setting GPIO as non-secure

Fixes STM32MP13 sequence that default configures GPIO as non-secure
from set_all_gpios_non_secure() registered at early_init_late initcall
level

plat-stm32mp1: fix default setting GPIO as non-secure

Fixes STM32MP13 sequence that default configures GPIO as non-secure
from set_all_gpios_non_secure() registered at early_init_late initcall
level, that is at same level driver are initially probed by dt_driver
framework. This result on set_all_gpios_non_secure() possibly needing
a bank resource before it is probed. Fix that by removing initcall
function set_all_gpios_non_secure() and default configuring GPIO pins
for STM32MP13 variant on their GPIO bank registering.

Fixes: 077d486ef09d ("drivers: stm32_gpio: add helper function stm32_gpio_get_bank()")
Acked-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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2fd102eb06-Jun-2023 Etienne Carriere <etienne.carriere@foss.st.com>

drivers: stm32_gpio: panic on clock enable error

Changes stm32_gpio.c to panic on bank clock gating error.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carrier

drivers: stm32_gpio: panic on clock enable error

Changes stm32_gpio.c to panic on bank clock gating error.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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1001585e26-May-2023 Etienne Carriere <etienne.carriere@foss.st.com>

drivers: stm32_gpio: remove GPIO access specific API functions

Removes stm32_gpio API functions to access GPIOs as the driver has
moved to the generic GPIO framework and consumer driver should use t

drivers: stm32_gpio: remove GPIO access specific API functions

Removes stm32_gpio API functions to access GPIOs as the driver has
moved to the generic GPIO framework and consumer driver should use the
generic API to access GPIOs. The driver now expects CFG_DRIVERS_GPIO
is enabled.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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ca1a94a130-May-2023 Etienne Carriere <etienne.carriere@foss.st.com>

plat-stm32mp1: enable CFG_DRIVERS_GPIO

Enables CFG_DRIVERS_GPIO for platform stm32mp1.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@

plat-stm32mp1: enable CFG_DRIVERS_GPIO

Enables CFG_DRIVERS_GPIO for platform stm32mp1.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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420a32c526-May-2023 Etienne Carriere <etienne.carriere@foss.st.com>

drivers: stm32_gpio: support CFG_DRIVERS_GPIO

Changes stm32_gpio driver to register GPIO provider resources for each
GPIO bank registered when CFG_DRIVERS_GPIO is enabled.

Acked-by: Gatien Chevalli

drivers: stm32_gpio: support CFG_DRIVERS_GPIO

Changes stm32_gpio driver to register GPIO provider resources for each
GPIO bank registered when CFG_DRIVERS_GPIO is enabled.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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a009881d05-Feb-2023 Etienne Carriere <etienne.carriere@linaro.org>

core: interrupt: add inline descriptions

Adds inline description comments in interrupt.h and fix an indentation.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carri

core: interrupt: add inline descriptions

Adds inline description comments in interrupt.h and fix an indentation.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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3475549b05-Feb-2023 Etienne Carriere <etienne.carriere@linaro.org>

core: interrupt: rename internal itr_chip to itr_main_chip

Renames local variable itr_chip into itr_main_chip to emphasize it is
the CPU main interrupt controller.

Reviewed-by: Jens Wiklander <jens

core: interrupt: rename internal itr_chip to itr_main_chip

Renames local variable itr_chip into itr_main_chip to emphasize it is
the CPU main interrupt controller.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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e050e0a731-May-2023 Etienne Carriere <etienne.carriere@linaro.org>

core: interrupt: interrupt_get_main_chip() returns main controller

Adds helper function interrupt_get_main_chip() to get the struct itr_chip
reference of the CPU main interrupt controller (e.g. the

core: interrupt: interrupt_get_main_chip() returns main controller

Adds helper function interrupt_get_main_chip() to get the struct itr_chip
reference of the CPU main interrupt controller (e.g. the GIC). This
function helps adapting a generic interrupt controller framework to
consider CPU main interrupt controller specific reference.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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145953d525-May-2023 Etienne Carriere <etienne.carriere@foss.st.com>

plat-stm32mp1: remove unused gpio bank base address helper function

Removes stm32mp1 platform helper function stm32_get_gpio_bank_base().

Acked-by: Lionel Debieve <lionel.debieve@foss.st.com>
Acked

plat-stm32mp1: remove unused gpio bank base address helper function

Removes stm32mp1 platform helper function stm32_get_gpio_bank_base().

Acked-by: Lionel Debieve <lionel.debieve@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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7c67e9ca25-May-2023 Etienne Carriere <etienne.carriere@foss.st.com>

plat-stm32mp1: remove unused gpio bank clock helper functions

Removes stm32mp1 platform helper functions stm32_get_gpio_bank_clock()
and stm32_get_gpio_bank_clk().

Acked-by: Lionel Debieve <lionel.

plat-stm32mp1: remove unused gpio bank clock helper functions

Removes stm32mp1 platform helper functions stm32_get_gpio_bank_clock()
and stm32_get_gpio_bank_clk().

Acked-by: Lionel Debieve <lionel.debieve@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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98dfceda31-May-2023 Etienne Carriere <etienne.carriere@foss.st.com>

drivers: stm32_gpio: don't mask interrupt during clock gating

Swaps interrupt masking and clock gating instructions to move GPIO
bank gating sequence outside of the time window when interrupt are
ma

drivers: stm32_gpio: don't mask interrupt during clock gating

Swaps interrupt masking and clock gating instructions to move GPIO
bank gating sequence outside of the time window when interrupt are
masked when the GPIO spinlock is locked.

Acked-by: Lionel Debieve <lionel.debieve@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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bed4582f30-May-2023 Etienne Carriere <etienne.carriere@foss.st.com>

drivers: stm32_gpio: use SHIFT_U32() where applicable

Replaces 32bit operand raw left shift with use of SHIFT_U32() macro.

Acked-by: Lionel Debieve <lionel.debieve@foss.st.com>
Acked-by: Gatien Che

drivers: stm32_gpio: use SHIFT_U32() where applicable

Replaces 32bit operand raw left shift with use of SHIFT_U32() macro.

Acked-by: Lionel Debieve <lionel.debieve@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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077d486e25-May-2023 Etienne Carriere <etienne.carriere@foss.st.com>

drivers: stm32_gpio: add helper function stm32_gpio_get_bank()

Adds helper function stm32_gpio_get_bank() in stm32_gpio to retrieve
a GPIO bank instance from the bank ID. This change will allow a la

drivers: stm32_gpio: add helper function stm32_gpio_get_bank()

Adds helper function stm32_gpio_get_bank() in stm32_gpio to retrieve
a GPIO bank instance from the bank ID. This change will allow a later
change to remove now useless platform helper functions
stm32_get_gpio_bank_base() and stm32_get_gpio_bank_clk().

This changes removes the verification of GPIO banks clock reference
against platform data (in ckeck_gpio_bank()) which is not really useful
as we can consider embedded DTB data are reliable.

Checks clk_enable() return value to panic on failure.

Acked-by: Lionel Debieve <lionel.debieve@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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f12b4ead02-Jun-2023 Etienne Carriere <etienne.carriere@foss.st.com>

drivers: pinctrl: pinctrl name may not be found

Changes pinctrl_get_state_by_name() to return TEE_ERROR_ITEM_NOT_FOUND
instead of TEE_ERROR_GENERIC when an pinctrl state index is not found
in the DT

drivers: pinctrl: pinctrl name may not be found

Changes pinctrl_get_state_by_name() to return TEE_ERROR_ITEM_NOT_FOUND
instead of TEE_ERROR_GENERIC when an pinctrl state index is not found
in the DT.

Fixes: 9aec039ec0d7 ("drivers: pinctrl: add pinctrl support")
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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52c31eb004-May-2023 Clement Faure <clement.faure@nxp.com>

drivers: ele: use the new derive key API for HUK generation

Use the derive key ELE API to generate the OPTEE HUK based on an input
pattern.
This change might break backward compatibility with pre-pr

drivers: ele: use the new derive key API for HUK generation

Use the derive key ELE API to generate the OPTEE HUK based on an input
pattern.
This change might break backward compatibility with pre-production
firmware revisions.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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92c2884f04-May-2023 Clement Faure <clement.faure@nxp.com>

drivers: ele: change RNG command ID

Change ELE API command ID for the RNG to 0xCD.
This change might break backward compatibility with pre-production
firmware revisions.

Signed-off-by: Clement Faur

drivers: ele: change RNG command ID

Change ELE API command ID for the RNG to 0xCD.
This change might break backward compatibility with pre-production
firmware revisions.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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322cf9e323-May-2023 Etienne Carriere <etienne.carriere@foss.st.com>

drivers: stm32_gpio: consider DT output data configuration

Get output data pin configuration from DT node property "output-high"
and "output-low".

Acked-by: Jerome Forissier <jerome.forissier@linar

drivers: stm32_gpio: consider DT output data configuration

Get output data pin configuration from DT node property "output-high"
and "output-low".

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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957f581a01-Jun-2023 Chia-Wei Wang <chiawei_wang@aspeedtech.com>

MAINTAINERS: Add Aspeed AST2700

Add maintainer for AST2700 SoC from Aspeed.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked

MAINTAINERS: Add Aspeed AST2700

Add maintainer for AST2700 SoC from Aspeed.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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ba69abea16-Feb-2023 Chia-Wei Wang <chiawei_wang@aspeedtech.com>

arm: Add Aspeed AST2700 platform support

Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 CPU.
This patch adds the platform support for AST2700 to execute
64-bits OP-TEE on top of ARMv8 TrustZo

arm: Add Aspeed AST2700 platform support

Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 CPU.
This patch adds the platform support for AST2700 to execute
64-bits OP-TEE on top of ARMv8 TrustZone features.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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0309f58d29-May-2023 Alvin Chang <alvinga@andestech.com>

scripts/symbolize.py: Support RISC-V architecture

If we get RISC-V architecture flag from ELF file, assign "self._arch" as
"riscv32-unknown-linux-gnu-" or "riscv64-unknown-linux-gnu-", since they
ar

scripts/symbolize.py: Support RISC-V architecture

If we get RISC-V architecture flag from ELF file, assign "self._arch" as
"riscv32-unknown-linux-gnu-" or "riscv64-unknown-linux-gnu-", since they
are prefixes of RISC-V's official toolchains.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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2e5a3b0d26-May-2023 Alvin Chang <alvinga@andestech.com>

core: riscv: Implement function to print kernel stack

Implement the function to print the kernel stack. The code is referenced
from ARM architecture.

Signed-off-by: Alvin Chang <alvinga@andestech.c

core: riscv: Implement function to print kernel stack

Implement the function to print the kernel stack. The code is referenced
from ARM architecture.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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4450510c26-May-2023 Alvin Chang <alvinga@andestech.com>

core: riscv: Add read_fp() and read_pc()

Implement inline functions to read PC and FP. This is required to trace
back the kernel stack.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by:

core: riscv: Add read_fp() and read_pc()

Implement inline functions to read PC and FP. This is required to trace
back the kernel stack.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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b498b83126-May-2023 Alvin Chang <alvinga@andestech.com>

core: riscv: Update the kernel mode unwinding

The data structure for RISC-V does not have sp, remove it in the
function. Also the function and structure are renamed.

Signed-off-by: Alvin Chang <alv

core: riscv: Update the kernel mode unwinding

The data structure for RISC-V does not have sp, remove it in the
function. Also the function and structure are renamed.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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27be144d26-May-2023 Alvin Chang <alvinga@andestech.com>

core: riscv: Add core compiler flags for stack unwinding

When the CFG_UNWIND is enabled, the frame pointer should not be omitted
by compiler. Add "-fno-omit-frame-pointer" compiler flag when we enab

core: riscv: Add core compiler flags for stack unwinding

When the CFG_UNWIND is enabled, the frame pointer should not be omitted
by compiler. Add "-fno-omit-frame-pointer" compiler flag when we enable
the CFG_UNWIND to let compiler not to omit the frame pointer.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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