MAINTAINERS: Add Aspeed AST2700

Add maintainer for AST2700 SoC from Aspeed.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked

MAINTAINERS: Add Aspeed AST2700

Add maintainer for AST2700 SoC from Aspeed.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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arm: Add Aspeed AST2700 platform support

Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 CPU.
This patch adds the platform support for AST2700 to execute
64-bits OP-TEE on top of ARMv8 TrustZo

arm: Add Aspeed AST2700 platform support

Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 CPU.
This patch adds the platform support for AST2700 to execute
64-bits OP-TEE on top of ARMv8 TrustZone features.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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scripts/symbolize.py: Support RISC-V architecture

If we get RISC-V architecture flag from ELF file, assign "self._arch" as
"riscv32-unknown-linux-gnu-" or "riscv64-unknown-linux-gnu-", since they
ar

scripts/symbolize.py: Support RISC-V architecture

If we get RISC-V architecture flag from ELF file, assign "self._arch" as
"riscv32-unknown-linux-gnu-" or "riscv64-unknown-linux-gnu-", since they
are prefixes of RISC-V's official toolchains.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Implement function to print kernel stack

Implement the function to print the kernel stack. The code is referenced
from ARM architecture.

Signed-off-by: Alvin Chang <alvinga@andestech.c

core: riscv: Implement function to print kernel stack

Implement the function to print the kernel stack. The code is referenced
from ARM architecture.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Add read_fp() and read_pc()

Implement inline functions to read PC and FP. This is required to trace
back the kernel stack.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by:

core: riscv: Add read_fp() and read_pc()

Implement inline functions to read PC and FP. This is required to trace
back the kernel stack.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Update the kernel mode unwinding

The data structure for RISC-V does not have sp, remove it in the
function. Also the function and structure are renamed.

Signed-off-by: Alvin Chang <alv

core: riscv: Update the kernel mode unwinding

The data structure for RISC-V does not have sp, remove it in the
function. Also the function and structure are renamed.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Add core compiler flags for stack unwinding

When the CFG_UNWIND is enabled, the frame pointer should not be omitted
by compiler. Add "-fno-omit-frame-pointer" compiler flag when we enab

core: riscv: Add core compiler flags for stack unwinding

When the CFG_UNWIND is enabled, the frame pointer should not be omitted
by compiler. Add "-fno-omit-frame-pointer" compiler flag when we enable
the CFG_UNWIND to let compiler not to omit the frame pointer.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Save and restore register s0 when trap occurs

In RISC-V the frame pointer is stored into register s0. It is necessary
to save/restore s0 when we enable CFG_UNWIND to process stack unwin

core: riscv: Save and restore register s0 when trap occurs

In RISC-V the frame pointer is stored into register s0. It is necessary
to save/restore s0 when we enable CFG_UNWIND to process stack unwinding.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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libunw: Implement RISC-V stack unwinding

This patch implements stack unwinding for RISC-V architecture into
libunw. In RISC-V, the caller stores its frame pointer into register
s0 before calling the

libunw: Implement RISC-V stack unwinding

This patch implements stack unwinding for RISC-V architecture into
libunw. In RISC-V, the caller stores its frame pointer into register
s0 before calling the function. In the prologue of callee function,
the return address and the caller's frame pointer are saved into the
bottom of the callee's stack frame, and the callee's frame pointer is
also calculated and stored into s0 within the process of callee
function. Therefore, the caller's stack frame can be traced back from
the callee's stack frame.

The following steps describe the stack unwinding on RV64 system:
1. When an exception occurs, we get the current frame pointer from
trapped register s0/fp.
2. Get the ra from the memory address (fp-0x8).
3. Get the caller's frame pointer from the memory address (fp-0x10).
4. Update the caller's pc as (ra-0x4), this is information we want from
stack unwinding.
5. Repeat the step 2 to step 4, until we exceed the stack frame of the
thread.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Correct sp before boot_init_primary_late()

Fix the stack pointer according to mentioned commits. The sp should be
assigned as thread#0's stack pointer, and the flag that indicates usage

core: riscv: Correct sp before boot_init_primary_late()

Fix the stack pointer according to mentioned commits. The sp should be
assigned as thread#0's stack pointer, and the flag that indicates usage
of the temporary stack must be cleared before boot_init_primary_late()
is called. After boot_init_primary_late() is returned, we restore the
previous sp and set the flag again.

Fixes: 59ac3801b756 ("core: split boot_init_primary()")
Fixes: 1d88c0c03f3b ("core: clear temporary stack flag before entering boot_init_primary_late()")'
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add plat-nuvoton

Adds support to Nuvoton npcm845x

Co-developed-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>
Signed-off-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>
Signed-off-

core: add plat-nuvoton

Adds support to Nuvoton npcm845x

Co-developed-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>
Signed-off-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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keys: rename the default key to default.pem

The default key can have other uses than the TA signature.
Rename the file to have a generic name.

For compatibility with existing code, doc and CI, the

keys: rename the default key to default.pem

The default key can have other uses than the TA signature.
Rename the file to have a generic name.

For compatibility with existing code, doc and CI, the
default_ta.pem is kept but becomes a symbolic link.

If the default_ta.pem is selected, the default.pem file is
also copied in the build folder as default_ta.pem symlink
points to it.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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ta: use TA_SIGN_KEY value for the key to copy for build

The default_ta.pem is copied whatever the key file used.
This leads to a build error if TA_SIGN_KEY is specified in the
build command.

Use th

ta: use TA_SIGN_KEY value for the key to copy for build

The default_ta.pem is copied whatever the key file used.
This leads to a build error if TA_SIGN_KEY is specified in the
build command.

Use the "TA_SIGN_KEY" value instead of hard-coding the key name.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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arm64: memtag: strip tag from crash dumps

The MTE tag is not really useful when displaying a crash dump. In fact
it makes it more complicated for tools like script/symbolize.py to
retrieve the actua

arm64: memtag: strip tag from crash dumps

The MTE tag is not really useful when displaying a crash dump. In fact
it makes it more complicated for tools like script/symbolize.py to
retrieve the actual (untagged) virtual address, especially as we now
support non-Arm architectures and therefore blindly stripping the MTE
bits is not possible.

This commit strips the tag in call stacks displayed by
print_stack_arm64(). It also removes it from the virtual address shown
on abort (__print_abort_info()) since symbolize.py does try to resolve
the address as symbol + offset ; but in this case the tagged address is
printed as well, because it can be helpful to diagnose tag check faults.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: rename dt_driver_phandle_args to dt_pargs

Renames struct dt_driver_phandle_args to struct dt_pargs to
shorten the label and prevent ugly line breaks in function
signatures.

Acked-by: Jens Wik

core: rename dt_driver_phandle_args to dt_pargs

Renames struct dt_driver_phandle_args to struct dt_pargs to
shorten the label and prevent ugly line breaks in function
signatures.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: spmc: configure SP's NS interrupt action based on the manifest

Use mandatory ns-interrupts-action SP manifest property to configure
signaled or queued non-secure interrupt handling.

Signed-of

core: spmc: configure SP's NS interrupt action based on the manifest

Use mandatory ns-interrupts-action SP manifest property to configure
signaled or queued non-secure interrupt handling.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: spmc: handle non-secure interrupts

Add FFA_INTERRUPT and FFA_RUN support for signaling non-secure
interrupts and for resuming to the secure world. If a secure partition
is preempted by a non-s

core: spmc: handle non-secure interrupts

Add FFA_INTERRUPT and FFA_RUN support for signaling non-secure
interrupts and for resuming to the secure world. If a secure partition
is preempted by a non-secure interrupt OP-TEE saves the SP's state and
sends an FFA_INTERRUPT to the normal world. After handling the interrupt
the normal world should send an FFA_RUN to OP-TEE so it can continue
running the SP.
If OP-TEE is the active FF-A endpoint (i.e. it is running TAs) the
non-secure interrupts are signaled by the existing
OPTEE_FFA_YIELDING_CALL_RETURN_INTERRUPT message instead of
FFA_INTERRUPT.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: gpio: add operation inline description

Adds few inline description comment to GPIO operators.

Acked-by: Thomas Perrot <thomas.perrot@bootlin.com>
Signed-off-by: Etienne Carriere <etienne.c

drivers: gpio: add operation inline description

Adds few inline description comment to GPIO operators.

Acked-by: Thomas Perrot <thomas.perrot@bootlin.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: gpio: add put operation handle

Adds a put operation handler for a GPIO consumer driver to be able
to release the GPIO resources it has allocated when getting its
GPIO. This is needed for ex

drivers: gpio: add put operation handle

Adds a put operation handler for a GPIO consumer driver to be able
to release the GPIO resources it has allocated when getting its
GPIO. This is needed for example, when such a consumer driver must defer
its probe sequence and will get again its GPIO making gpio_dt_alloc_pin()
to be called again.

Acked-by: Thomas Perrot <thomas.perrot@bootlin.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: add missing inclusion of stm32_gpio.h

Adds inclusion of stm32_gpio.h from main.c that is needed when
CFG_STM32MP13 is enabled.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org

plat-stm32mp1: add missing inclusion of stm32_gpio.h

Adds inclusion of stm32_gpio.h from main.c that is needed when
CFG_STM32MP13 is enabled.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_rng: fix case when RNG is not ready

Checks RNG data ready status bit before each read of a 32bit
sample from the RNG FIFO. Indeed the data ready status bit tells that
the RNG FIFO con

drivers: stm32_rng: fix case when RNG is not ready

Checks RNG data ready status bit before each read of a 32bit
sample from the RNG FIFO. Indeed the data ready status bit tells that
the RNG FIFO contains random bytes by burst of 32bit word,
not by burst of 4 32bit words.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: remove unused stm32mp_gpio_bank_is_shared()

Removes platform function stm32mp_gpio_bank_is_shared() that is not
used.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-b

plat-stm32mp1: remove unused stm32mp_gpio_bank_is_shared()

Removes platform function stm32mp_gpio_bank_is_shared() that is not
used.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: fix driver header file guards

Fixes the names of the macro used as stm32_gpio.h header file guard.

Acked-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne

drivers: stm32_gpio: fix driver header file guards

Fixes the names of the macro used as stm32_gpio.h header file guard.

Acked-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: probe pinctrl nodes

This change makes stm32_gpio driver to register GPIO bank when the
driver of probed on compatible pin control instances found in the
device tree. This change

drivers: stm32_gpio: probe pinctrl nodes

This change makes stm32_gpio driver to register GPIO bank when the
driver of probed on compatible pin control instances found in the
device tree. This change however does not yet register pinctrl
providers to DT_DRIVER framework.

Acked-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: helper function to register GPIO banks

Adds an helper function (dt_stm32_gpio_bank()) to register GPIO banks
in stm32_gpio driver based on DT pinctrl nodes. GPIO banks are
regis

drivers: stm32_gpio: helper function to register GPIO banks

Adds an helper function (dt_stm32_gpio_bank()) to register GPIO banks
in stm32_gpio driver based on DT pinctrl nodes. GPIO banks are
registered in a local list from which will be later used to find a
bank based on its ID number. The function is expected to be called
from the driver probe sequence. The function ensures a bank is not
registered twice.

Acked-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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