| c16aaf42 | 01-Sep-2023 |
Clement Faure <clement.faure@nxp.com> |
drivers: pm: imx: relocate power management code
Relocate power management functions from plat-imx/pm to core/drivers/pm/imx
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wikl
drivers: pm: imx: relocate power management code
Relocate power management functions from plat-imx/pm to core/drivers/pm/imx
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| e7778701 | 07-Sep-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: re-work GPCv2 driver
Re-work GPCv2 driver: * use io_clr/set functions * use timeout for register polling Remove imx_gpcv2_set_core1_pdn_by_software() function.
Signed-off-by: Clement F
core: imx: re-work GPCv2 driver
Re-work GPCv2 driver: * use io_clr/set functions * use timeout for register polling Remove imx_gpcv2_set_core1_pdn_by_software() function.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 068596e0 | 31-Aug-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: move gpcv2 functions definitions to local.h
Move imx_gpcv2_set_core1_pdn_by_software() and imx_gpcv2_set_core1_pup_by_software() definitions to local.h. Make imx_gpcv2_set_core_pgc() stat
core: imx: move gpcv2 functions definitions to local.h
Move imx_gpcv2_set_core1_pdn_by_software() and imx_gpcv2_set_core1_pup_by_software() definitions to local.h. Make imx_gpcv2_set_core_pgc() static.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 255a1fb9 | 30-Aug-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: cleanup imx-regs.h
Remove macros from imx-regs.h and relocate to appropriate source files.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@l
core: imx: cleanup imx-regs.h
Remove macros from imx-regs.h and relocate to appropriate source files.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 11c218db | 30-Aug-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: move PSCI SNVS operation to the driver
Create imx_snvs_shutdown() to use during psci_system_off() call.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jen
core: imx: move PSCI SNVS operation to the driver
Create imx_snvs_shutdown() to use during psci_system_off() call.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 2d75eb94 | 30-Aug-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: fix IOMUXC GPR5 register read
Define IOMUXC_SIZE value for imx7 platforms and re-work the way the GPR register is read.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jen
core: imx: fix IOMUXC GPR5 register read
Define IOMUXC_SIZE value for imx7 platforms and re-work the way the GPR register is read.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 3ef1e5ae | 30-Aug-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: re-work SRC driver
Encapsulate all SRC register operations in dedicated functions. Move SRC register offsets and values to SRC source file. Define SRC_SIZE for i.MX6 and i.MX7 platforms.
core: imx: re-work SRC driver
Encapsulate all SRC register operations in dedicated functions. Move SRC register offsets and values to SRC source file. Define SRC_SIZE for i.MX6 and i.MX7 platforms.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| c24517c5 | 30-Aug-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: move SRC driver to pm directory
Move the SRC driver to pm sub-directory since it is related to the power management PSCI features. Rename it from imx_src.c to src.c. Create a local header
core: imx: move SRC driver to pm directory
Move the SRC driver to pm sub-directory since it is related to the power management PSCI features. Rename it from imx_src.c to src.c. Create a local header file.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| cd5843ae | 30-Aug-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: remove PSCI_CPU_SUSPEND capability
Remove the PSCI_CPU_SUSPEND capability as it is not supported.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wikl
core: imx: remove PSCI_CPU_SUSPEND capability
Remove the PSCI_CPU_SUSPEND capability as it is not supported.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 4c603f28 | 30-Aug-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: remove power management code for imx7d platforms
The code for suspend and cpuidle is not functioning properly, outdated and unmaintained. Remove these two features and associated code.
S
core: imx: remove power management code for imx7d platforms
The code for suspend and cpuidle is not functioning properly, outdated and unmaintained. Remove these two features and associated code.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 68045ae9 | 25-Sep-2023 |
Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> |
scripts: sign_rproc_fw: clean up unused TLV method
Remove the __len__ method of the TLV class. It is not being used and uses an undefined variable TLV_INFO_SIZE. This method is a remnant of code tha
scripts: sign_rproc_fw: clean up unused TLV method
Remove the __len__ method of the TLV class. It is not being used and uses an undefined variable TLV_INFO_SIZE. This method is a remnant of code that was removed during upstream reviews.
Fixes: e8ef53536bda ("scripts: add remote processor firmware signature tool") Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 623b9bd4 | 23-Aug-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: use monotonic counter for secure storage without RPMB
If OP-TEE is configured without RPMB (CFG_REE_FS_INTEGRITY_RPMB=n), use the non-volatile monotonic counter interface instead to protect ag
core: use monotonic counter for secure storage without RPMB
If OP-TEE is configured without RPMB (CFG_REE_FS_INTEGRITY_RPMB=n), use the non-volatile monotonic counter interface instead to protect against rollback of the REE FS base secure storage.
If configured without CFG_WARN_INSECURE=y, accept TEE_ERROR_NOT_IMPLEMENTED error from nv_counter_get_ree_fs() and nv_counter_incr_ree_fs_to() and warn once to make clear that the configuration isn't secure.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Tested-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 200cc96d | 23-Aug-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add non-volatile monotonic counter interface
Adds a stubbed non-volatile monotonic counter interface with a REE FS counter. Platforms or drivers overrides the weak functions nv_counter_get_ree
core: add non-volatile monotonic counter interface
Adds a stubbed non-volatile monotonic counter interface with a REE FS counter. Platforms or drivers overrides the weak functions nv_counter_get_ree_fs() and nv_counter_incr_ree_fs_to() to provide a non-stubbed implementation of the counter.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 57b21489 | 30-Aug-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: tee: add entry_fast.c
This commit adds an implementation of fast call handers. It copies the original implementation replacing thread_smc_args structures with thread_abi_args counterpar
core: riscv: tee: add entry_fast.c
This commit adds an implementation of fast call handers. It copies the original implementation replacing thread_smc_args structures with thread_abi_args counterparts. tee_entry_fastcall_l2cc_mutex() has been modified to return OPTEE_ABI_RETURN_UNKNOWN_FUNCTION.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Tested-by: Alvin Chang <alvinga@andestech.com>
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| 5cc48b15 | 29-Aug-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: add thread_optee_abi.c
This commit just copies thread_optee_smc.c from ARM and renames smc/SMC to abi/ABI.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alv
core: riscv: add thread_optee_abi.c
This commit just copies thread_optee_smc.c from ARM and renames smc/SMC to abi/ABI.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Tested-by: Alvin Chang <alvinga@andestech.com>
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| 55dd28e8 | 29-Aug-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: include: add tee/teeabi_opteed_macros.h
This commit just copies teesmc_opteed_macros.h from ARM and renames smc/SMC to abi/ABI. All unused and ARM-related macros are removed.
Signed-of
core: riscv: include: add tee/teeabi_opteed_macros.h
This commit just copies teesmc_opteed_macros.h from ARM and renames smc/SMC to abi/ABI. All unused and ARM-related macros are removed.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Tested-by: Alvin Chang <alvinga@andestech.com>
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| 14812c66 | 29-Aug-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: include: add tee/teeabi_opteed.h
This commit just copies teesmc_opteed.h from ARM and renames smc/SMC to abi/ABI.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-
core: riscv: include: add tee/teeabi_opteed.h
This commit just copies teesmc_opteed.h from ARM and renames smc/SMC to abi/ABI.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Tested-by: Alvin Chang <alvinga@andestech.com>
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| 21c10a52 | 29-Aug-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: include: add tee/optee_abi.h
This commit just copies optee_smc.h from ARM and renames smc/SMC to abi/ABI.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvi
core: riscv: include: add tee/optee_abi.h
This commit just copies optee_smc.h from ARM and renames smc/SMC to abi/ABI.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Tested-by: Alvin Chang <alvinga@andestech.com>
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| a12b98e3 | 29-Aug-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: include: add tee/entry_fast.h
This commit just copies entry_fast.h from ARM and renames thread_smc_args to thread_abi_args.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
core: riscv: include: add tee/entry_fast.h
This commit just copies entry_fast.h from ARM and renames thread_smc_args to thread_abi_args.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Tested-by: Alvin Chang <alvinga@andestech.com>
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| a2efa71b | 29-Aug-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: move TEE ABI handlers from thread_rv.S to thread_optee_abi_rv.S
This commits moves the following functions from thread_rv.S to a separate file thread_optee_abi_rv.S:
- thread_return_fr
core: riscv: move TEE ABI handlers from thread_rv.S to thread_optee_abi_rv.S
This commits moves the following functions from thread_rv.S to a separate file thread_optee_abi_rv.S:
- thread_return_from_nsec_call() - thread_std_smc_entry() -> renamed to thread_std_abi_entry() - thread_rpc()
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Tested-by: Alvin Chang <alvinga@andestech.com>
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| 3f1a58ff | 29-Aug-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: thread_arch.c: Use of ABI structure instead of SMC structure
SMC is an ARM-related keyword, make use thread_std_abi_entry instead of thread_std_smc_entry.
Signed-off-by: Marouene Bouba
core: riscv: thread_arch.c: Use of ABI structure instead of SMC structure
SMC is an ARM-related keyword, make use thread_std_abi_entry instead of thread_std_smc_entry.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Tested-by: Alvin Chang <alvinga@andestech.com>
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| b0f61f0c | 29-Aug-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: thread_private_arch.h: add std and fast calls prototypes
This commit adds the following prototypes to thread_private_arch.h: - thread_std_abi_entry() - __thread_std_abi_entry() - thread
core: riscv: thread_private_arch.h: add std and fast calls prototypes
This commit adds the following prototypes to thread_private_arch.h: - thread_std_abi_entry() - __thread_std_abi_entry() - thread_handle_fast_abi() - thread_handle_std_abi()
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Tested-by: Alvin Chang <alvinga@andestech.com>
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| 4d941774 | 29-Aug-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: thread_arch.h: rename thread_smc_args to thread_abi_args
SMC is an ARM-related keyword referring to Secure Monitor Call. This commit renames thread_smc_args to thread_abi_args in thread
core: riscv: thread_arch.h: rename thread_smc_args to thread_abi_args
SMC is an ARM-related keyword referring to Secure Monitor Call. This commit renames thread_smc_args to thread_abi_args in thread_arch.h and keeps the same members to guarantee compatibility with the existing secure and non-secure domain communication protocol.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Tested-by: Alvin Chang <alvinga@andestech.com>
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| 9240925f | 24-Aug-2023 |
Andrew Davis <afd@ti.com> |
plat-k3: Default to 2 core per cluster only for AM65x
All other SoCs have 4 cores per cluster, which is the default, or they only have one cluster in which case this value is unimportant.
Signed-of
plat-k3: Default to 2 core per cluster only for AM65x
All other SoCs have 4 cores per cluster, which is the default, or they only have one cluster in which case this value is unimportant.
Signed-off-by: Andrew Davis <afd@ti.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 5f1edb13 | 20-Sep-2023 |
Balint Dobszay <balint.dobszay@arm.com> |
core: sp: fix raw binary format SP loader
Loading a compressed raw binary format SP fails when read_compressed() in embedded_ts.c is trying to allocate memory using bb_alloc(), since the bounce buff
core: sp: fix raw binary format SP loader
Loading a compressed raw binary format SP fails when read_compressed() in embedded_ts.c is trying to allocate memory using bb_alloc(), since the bounce buffer in this user_mode_ctx is uninitialized. For ELF format SPs ldelf is taking care of this, let's add the necessary initialization to the raw binary format loader too.
Fixes: ef44161f847b ("core: update ts_store API with user space buffer") Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
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