Update CHANGELOG for 4.2.0

Update CHANGELOG for 4.2.0 and collect Tested-by tags.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@foss.st.com> (stm

Update CHANGELOG for 4.2.0

Update CHANGELOG for 4.2.0 and collect Tested-by tags.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@foss.st.com> (stm32mp1-135F_DK w/ pkcs11)
Tested-by: Etienne Carriere <etienne.carriere@foss.st.com> (stm32mp1-157C_DK2_SCMI w/ pkcs11)
Tested-by: Etienne Carriere <etienne.carriere@foss.st.com> (stm32mp1-157C_EV1 w/ RPMB)
Tested-by: Imre Kis <imre.kis@arm.com> (fvp-ts)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (imx-mx8mqevk)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (rockchip-rk3399) (Rockpi4B)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_virt)
Tested-by: Joakim Bech <joakim.bech@linaro.org> (RPi 3B v1.2)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx6dlsabresd)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx6qsabresd)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx6sllevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx6ulevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx6ulzevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx7dsabresd)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx7ulpevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8dxlevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8mmevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8mnevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8mpevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8mqevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8qmmek)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8qxpmek)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8ulpevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx93evk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1012A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1046A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LX2160A-RDB)

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plat-sam: add support for Microchip sama7g54-ek board

Add the main functions for sama7g54 initialize, including:
- console_init()
- Matrix, TZC, TZPM, interrupt related
Update conf.mk and Makefile

plat-sam: add support for Microchip sama7g54-ek board

Add the main functions for sama7g54 initialize, including:
- console_init()
- Matrix, TZC, TZPM, interrupt related
Update conf.mk and Makefile for sama7g5 OP-TEE support.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: rename filename for sama5d2 functions to 'platform_sama5d2.c'

Rename 'main.c' to 'platform_sama5d2.c' in 'core/arch/arm/plat-sam'.
Update the makefile accordingly.

Signed-off-by: Tony Han

plat-sam: rename filename for sama5d2 functions to 'platform_sama5d2.c'

Rename 'main.c' to 'platform_sama5d2.c' in 'core/arch/arm/plat-sam'.
Update the makefile accordingly.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: optimize the macro and makefile for building sama5d2 clocks

Rename 'CFG_DRIVERS_SAMA5D2_CLK' to 'CFG_SAMA5D2'.
Adjust the sequence of source files in 'core/drivers/clk/sam/sub.mk'.

Signed

plat-sam: optimize the macro and makefile for building sama5d2 clocks

Rename 'CFG_DRIVERS_SAMA5D2_CLK' to 'CFG_SAMA5D2'.
Adjust the sequence of source files in 'core/drivers/clk/sam/sub.mk'.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_wdt: update "#include" list of the header files

Remove the unused header files from "#include".
"#include" the header files needed explicitly even if they are included
indirectly.

Si

drivers: atmel_wdt: update "#include" list of the header files

Remove the unused header files from "#include".
"#include" the header files needed explicitly even if they are included
indirectly.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_wdt: remove the unused variable from "struct atmel_wdt"

The variable "unsigned long rate" is not used, remove it.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Fo

drivers: atmel_wdt: remove the unused variable from "struct atmel_wdt"

The variable "unsigned long rate" is not used, remove it.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_wdt: upgrade to support sama7g5 watchdog

In sama7g5 there's a DWDT (Dual Watchdog Timer) and the registers
are not the same as the wdt for sama5d2. Here the DWD is handled
as 2 watchd

drivers: atmel_wdt: upgrade to support sama7g5 watchdog

In sama7g5 there's a DWDT (Dual Watchdog Timer) and the registers
are not the same as the wdt for sama5d2. Here the DWD is handled
as 2 watchdogs.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: reset cancellation mask on TA exit

Before this patch, the TA cancellation mask was only reset when the
session was created, but the GP spec requires the cancellation mask to
be reset each time

core: reset cancellation mask on TA exit

Before this patch, the TA cancellation mask was only reset when the
session was created, but the GP spec requires the cancellation mask to
be reset each time a TA is entered via one of its entry points. So fix
this by resetting the cancellation mask each time a TA returns.

Link: https://github.com/OP-TEE/optee_test/issues/731
Fixes: b01047730e77 ("Open-source the TEE Core")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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ci: add QEMUv7 job

Add a job to build and run tests with QEMU for Arm v7 (32-bit). The
build flags are imported from the IBART job definition [1] since
IBART is being deprecated. CFG_ENABLE_EMBEDDED

ci: add QEMUv7 job

Add a job to build and run tests with QEMU for Arm v7 (32-bit). The
build flags are imported from the IBART job definition [1] since
IBART is being deprecated. CFG_ENABLE_EMBEDDED_TESTS=n is dropped
however.

The job uses a new container image from the Docker Hub:
jforissier/optee_os_ci:qemu_check [2]. The source code (Dockerfile)
is at [3]. It is almost the same as the one used for QEMUv8
(jforissier/optee_os_ci:qemuv8_check2) except that
it contains a more generic "get_optee.sh [<platform>] [<destination>]"
script (which can clone any patform) and also includes two missing
packages that are required for QEMUv7 build (libgmp-dev and libmpc-dev).
The QEMUv8 jobs will be updated to switch to the newer image in a
subsequent commit.

Link: https://github.com/jbech-linaro/ibart/blob/b585163626341864790398df6489c9556e0b20f1/jobdefs/examples/optee_qemu.yaml#L40C26-L40C176 [1]
Link: https://hub.docker.com/r/jforissier/optee_os_ci/tags?page=1&name=qemu_check [2]
Link: https://github.com/jforissier/docker_optee_os_ci/tree/qemu_check [3]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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vexpress-qemu_armv8a: increase CFG_CORE_HEAP_SIZE to 131072

Set the default core heap size for QEMUv8 to 128K because 64K is not
enough to complete the "make check" test with CFG_RPMB_FS=y
CFG_RPMB_

vexpress-qemu_armv8a: increase CFG_CORE_HEAP_SIZE to 131072

Set the default core heap size for QEMUv8 to 128K because 64K is not
enough to complete the "make check" test with CFG_RPMB_FS=y
CFG_RPMB_WRITE_KEY=y.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: stm32_i2c: protect bus access with a mutex

Protect concurrent accesses to an STM32 I2C bus with a PM aware mutex.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by:

drivers: stm32_i2c: protect bus access with a mutex

Protect concurrent accesses to an STM32 I2C bus with a PM aware mutex.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: stm32_rifsc: remove use of CFG_PM

Remove use of CFG_PM from STM32 RIFSC driver since this configuration
switch is not defined in OP-TEE OS.

Reviewed-by: Gatien Chevallier <gatien

drivers: firewall: stm32_rifsc: remove use of CFG_PM

Remove use of CFG_PM from STM32 RIFSC driver since this configuration
switch is not defined in OP-TEE OS.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rng: remove use of CFG_PM

Remove use of CFG_PM from STM32 RNG driver since this configuration
switch is not defined in OP-TEE OS.

Reviewed-by: Gatien Chevallier <gatien.chevallier@fo

drivers: stm32_rng: remove use of CFG_PM

Remove use of CFG_PM from STM32 RNG driver since this configuration
switch is not defined in OP-TEE OS.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32_cryp: add pm to CRYP driver

Add power management support to the CRYP driver through suspend/resume
callbacks.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Sig

drivers: crypto: stm32_cryp: add pm to CRYP driver

Add power management support to the CRYP driver through suspend/resume
callbacks.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32_cryp: add delay when resetting CRYP peripheral.

Add 2 us of delay between reset assert and reset deassert to ensure the
peripheral is properly reset.

Signed-off-by: Thomas Bo

drivers: crypto: stm32_cryp: add delay when resetting CRYP peripheral.

Add 2 us of delay between reset assert and reset deassert to ensure the
peripheral is properly reset.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32_cryp: remove reset binding requirements

Remove panic during probe when "resets" property is not found because
it's optional in most cases.

Signed-off-by: Thomas Bourgoin <tho

drivers: crypto: stm32_cryp: remove reset binding requirements

Remove panic during probe when "resets" property is not found because
it's optional in most cases.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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ci.yml: add a make command to build HPRE code

Add a make command of CFG_HISILICON_ACC_V3=y

Signed-off-by: loubaihui <loubaihui1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

ci.yml: add a make command to build HPRE code

Add a make command of CFG_HISILICON_ACC_V3=y

Signed-off-by: loubaihui <loubaihui1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: hisilicon: init HPRE hardware block

The HiSilicon HPRE is a High Performance RSA Engine.
This module implement the hardware initialization of
the HPRE.

Signed-off-by: loubaihui <lo

drivers: crypto: hisilicon: init HPRE hardware block

The HiSilicon HPRE is a High Performance RSA Engine.
This module implement the hardware initialization of
the HPRE.

Signed-off-by: loubaihui <loubaihui1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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ci: remame WD to OPTEE_OS_TO_TEST

WD is not a very good variable name, it stands for "working directory"
but does not express what this directory contains. Use OPTEE_OS_TO_TEST
instead, since it is

ci: remame WD to OPTEE_OS_TO_TEST

WD is not a very good variable name, it stands for "working directory"
but does not express what this directory contains. Use OPTEE_OS_TO_TEST
instead, since it is actually the optee_os directory checked out by CI
(i.e., the current branch or PR to test).

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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ci: update QEMUv8 jobs to use newer Docker image

Update the QEMUv8 jobs to use the newer Docker image:
jforissier/optee_os_ci:qemu_check, which has a more generic script to
clone the OP-TEE environm

ci: update QEMUv8 jobs to use newer Docker image

Update the QEMUv8 jobs to use the newer Docker image:
jforissier/optee_os_ci:qemu_check, which has a more generic script to
clone the OP-TEE environment [1].

Link: https://github.com/jforissier/docker_optee_os_ci/blob/qemu_check/get_optee.sh [1]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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core: kernel: Fix typo in __do_panic()

Must be "preemption" instead of "prehemption".

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

drivers: regulator: use mutex_pm_aware

Use newly introduced struct mutex_pm_aware semaphore to protect
regulator accesses.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Eti

drivers: regulator: use mutex_pm_aware

Use newly introduced struct mutex_pm_aware semaphore to protect
regulator accesses.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: replace clock main spinlock with a mutex

Change clock framework lock from an interrupts masked spinning lock
to a mutex. This allows the clock framework to better handle slow
stabilizi

drivers: clk: replace clock main spinlock with a mutex

Change clock framework lock from an interrupts masked spinning lock
to a mutex. This allows the clock framework to better handle slow
stabilizing clocks as PLLs without masking the system interrupt
which can have side effects on the REE or even the TEE.

To support clock accesses during low power state transition sequences
while non-secure world is no operating, the lock is not taken when
the execution is not in the scope of a TEE thread.

This change is not expected to impact supported platforms that currently
only access clock operation from thread contexts or atomic PM sequences.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: kernel: mutex compliant with PM sequences

Add mutex_pm_aware_*() functions for mutex used on resources accessed
at runtime using a conventional mutex and also during low power
sequences that e

core: kernel: mutex compliant with PM sequences

Add mutex_pm_aware_*() functions for mutex used on resources accessed
at runtime using a conventional mutex and also during low power
sequences that execute in a non-thread context.

This change defines MUTEX_PM_AWARE_INITIALIZER macro from a new
header file (mutex_pm_aware.h) instead of existing mutex.h to prevent
a circular dependency between spinlock.h (requires thread.h), thread.h
(indirectly includes mutex.h) and mutex.h (that would depend on
spinlock.h for definition of the SPINLOCK_UNLOCK macro ).

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: kernel: thread spin locking

Add thread_spin_lock() and thread_spin_unlock() for active spinning
locks in situation where we need an exclusive lock in a thread and
interruptible context even at

core: kernel: thread spin locking

Add thread_spin_lock() and thread_spin_unlock() for active spinning
locks in situation where we need an exclusive lock in a thread and
interruptible context even at the cost of a high CPU usage.

These function are intended to be used in thread context hence
they assert being executed in such a context. This is to prevent
on mistakenly spin in an atomic context which potentially leads
to a deadlock situation.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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