| a51d45b5 | 17-Dec-2021 |
Jens Wiklander <jens.wiklander@linaro.org> |
libutils: mempool based raw malloc functions
Instead of the old stack like internal memory allocator, use the raw
malloc functions instead for more efficient memory usage.
CFG_WITH_STATS is enabled
libutils: mempool based raw malloc functions
Instead of the old stack like internal memory allocator, use the raw
malloc functions instead for more efficient memory usage.
CFG_WITH_STATS is enabled automatically if
CFG_MEMPOOL_REPORT_LAST_OFFSET is enabled to secure a new dependency in
the code.
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| c2d44948 | 20-Apr-2021 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add asynchronous notifications
Adds support for asynchronous notifications from secure world to normal
world. This allows a design with a top half and bottom half type of
driver where the top
core: add asynchronous notifications
Adds support for asynchronous notifications from secure world to normal
world. This allows a design with a top half and bottom half type of
driver where the top half runs in secure interrupt context and a
notifications tells normal world to schedule a yielding call to do the
bottom half processing.
The protocol is defined in optee_msg.h optee_rpc_cmd.h and optee_smc.h.
A notification consists of a 32-bit value which normal world can
retrieve using a fastcall into secure world. OP-TEE is currently only
supporting the value 0-63 where 0 has a special meaning. When 0 is sent
it means that normal world is supposed to make a yielding call
OPTEE_MSG_CMD_DO_BOTTOM_HALF.
The notification framework in OP-TEE defines an interface where drivers
can register a callback which is called on each yielding bottom half
call.
Notification capability is negotiated with the normal world while it
initializes its driver. If both sides supports these notifications then
they are enabled.
CFG_CORE_ASYNC_NOTIF_GIC_INTID is added to define the hardware interrupt
used to notify normal world. This is added to the DTB in case OP-TEE can
is configured with CFG_DT=y. Other cases requires the normal world DTB
to be kept in sync with this.
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| b7a623f8 | 02-Nov-2021 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
config: Add config options to enable BTI for TEE core and TA's
Branch Target Identification (part of the ARMv8.5 Extensions)
provides a mechanism to limit the set of locations to which
computed bran
config: Add config options to enable BTI for TEE core and TA's
Branch Target Identification (part of the ARMv8.5 Extensions)
provides a mechanism to limit the set of locations to which
computed branch instructions such as BR or BLR can jump.
To make use of BTI in TEE cores and ldelf on CPU's that
support it, enable the option CFG_CORE_BTI. The option is only
supported for ARM64 cores.
To enable BTI support for TA's and user mode libraries,
enable the option CFG_TA_BTI.
The BTI support is currently not compatible with options
CFG_VIRTUALIZATION and CFG_WITH_PAGER.
To use the option CFG_CORE_BTI, GCC toolchain built with
--enable-standard-branch-protection is needed.
To test with QEMU, use option -cpu max,sve=off.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jerome Forissier <jerome@forissier.org> (vexpress-qemu_armv8a)
show more ...
|
| 48685b6c | 16-Dec-2021 |
Jerome Forissier <jerome@forissier.org> |
arm64: bti: fail link phase if some objects do not support BTI
Adds the proper linker options (-z force-bti --fatal-warnings) to fail
the link if some object files lack the BTI feature bit when BTI
arm64: bti: fail link phase if some objects do not support BTI
Adds the proper linker options (-z force-bti --fatal-warnings) to fail
the link if some object files lack the BTI feature bit when BTI is
requested (CFG_CORE_BTI=Y, CFG_TA_BTI=y). The options are added for
tee.elf, ldelf.elf, in-tree TAs, in-tree user space shared libraries
(CFG_ULIBS_SHARED=y) as well as for external TAs and shared libraries
built with the dev kit.
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Ruchika Gupta <ruchika.gupta@linaro.org>
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|
| 07fda6c7 | 29-Nov-2021 |
Jerome Forissier <jerome@forissier.org> |
build: introduce _CFG_WITH_SECURE_STORAGE
Adds _CFG_WITH_SECURE_STORAGE set to 'y' when at least one secure
storage backend is enabled.
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Review
build: introduce _CFG_WITH_SECURE_STORAGE
Adds _CFG_WITH_SECURE_STORAGE set to 'y' when at least one secure
storage backend is enabled.
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| 33b38f8c | 21-Nov-2021 |
Ruslan Piasetskyi <ruslan.piasetskyi@gmail.com> |
core: introduce CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID
Adds CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID which if set to 'y' makes
huk_subkey_derive() generate SSK using tee_otp_get_die_id().
Old s
core: introduce CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID
Adds CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID which if set to 'y' makes
huk_subkey_derive() generate SSK using tee_otp_get_die_id().
Old scheme for SSK generation:
SSK = HMAC_SHA256(HUK, Chip_ID || "ONLY_FOR_tee_fs_ssk")
This config changes Chip_ID from the default BEEF-like value to the
result of tee_otp_get_die_id().
Note that this option works only if
CFG_CORE_HUK_SUBKEY_COMPAT=y.
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Ruslan Piasetskyi <ruslan.piasetskyi@gmail.com>
show more ...
|
| a748f9ed | 24-Nov-2021 |
Jens Wiklander <jens.wiklander@linaro.org> |
Add config option CFG_WARN_DECL_AFTER_STATEMENT
Adds configuration option CFG_WARN_DECL_AFTER_STATEMENT which adds the
warning -Wdeclaration-after-statement.
The coding style doesn't allow declarat
Add config option CFG_WARN_DECL_AFTER_STATEMENT
Adds configuration option CFG_WARN_DECL_AFTER_STATEMENT which adds the
warning -Wdeclaration-after-statement.
The coding style doesn't allow declarations after statements in the
code. So add a warning for this to let the compiler catch this before
the review.
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 9e42008d | 22-Nov-2021 |
Joakim Bech <joakim.bech@linaro.org> |
config: add flag CFG_WARN_INSECURE
OP-TEE is a reference implementation for developers and device
manufacturers, which implies that there always is a need to fill in
missing pieces that cannot be do
config: add flag CFG_WARN_INSECURE
OP-TEE is a reference implementation for developers and device
manufacturers, which implies that there always is a need to fill in
missing pieces that cannot be done generically. The chipmakers often
have additional security configurations those needs to be configured
according to the chipmakers security guidelines and security
specifications.
To reduce the likelihood of running a vanilla configured OP-TEE we
introduce the flag CFG_WARN_INSECURE that will give warning messages in
the boot saying that the OP-TEE runs a configuration that might be
insecure. The intention is that the device manufacturer making the end
products should change the flag to "n" after implementing stubbed
functionality in OP-TEE and configuring their device according to the
chipmakers security guidelines and security specifications.
Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| 804e32d7 | 14-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: clk: add fixed-clock driver
fixed-clock are a really common clock types used in device tree and
when there is a clock hierarchy, they are needed to query the clock
rate. This driver is buil
drivers: clk: add fixed-clock driver
fixed-clock are a really common clock types used in device tree and
when there is a clock hierarchy, they are needed to query the clock
rate. This driver is build by default when CFG_DRIVERS_CLK_DT is
enabled.
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
show more ...
|
| dbe94a85 | 25-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: clk: add devicetree support
When using a devicetree, it is often useful to have clocks parsing.
This support adds clocks properties parsing and allow having clock
providers and users. Clock
drivers: clk: add devicetree support
When using a devicetree, it is often useful to have clocks parsing.
This support adds clocks properties parsing and allow having clock
providers and users. Clocks drivers can also be declared with
CLK_DT_DECLARE. They will be probed automatically by the clock core.
On the user side, function clk_dt_get_by_name and clk_dt_get_by_idx
allows to retrieve a clock from the device tree description and match
it with the provider clocks. The core ensure the clocks are probed
hierarchically.
This support is enabled using CFG_DRIVERS_CLK_DT.
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
show more ...
|
| 2305544b | 10-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: clk: add generic clock framework
In order to ease clock support in OP-TEE, add a generic clock framework
which allows to add clocks driver and handle clock hierarchy.
This clock framework p
drivers: clk: add generic clock framework
In order to ease clock support in OP-TEE, add a generic clock framework
which allows to add clocks driver and handle clock hierarchy.
This clock framework provides various functions to enable/disable clock
and to get their rate. Some basic behavior are supported such as gating
when parent or rate is set. This option is enabled using
CFG_DRIVERS_CLK which is disabled by default.
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
show more ...
|
| 6be0dbca | 24-Sep-2021 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
Update CHANGELOG for 3.15.0
Update CHANGELOG for 3.15.0 and collect Tested-by tags.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6
Update CHANGELOG for 3.15.0
Update CHANGELOG for 3.15.0 and collect Tested-by tags.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qpsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sllevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sxsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ullevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulzevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7dsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7ulpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mmevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mnevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mqevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qmmek)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qxpmek)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_DK2 gp pkcs11)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_EV1 gp pkcs11 StMM)
Tested-by: Igor Opaniuk <igor.opaniuk@foundries.io> (Poplar)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (imx-mx8mqevk)
Tested-by: Jerome Forissier <jerome@forissier.org> (hikey-hikey)
Tested-by: Jerome Forissier <jerome@forissier.org> (hikey-hikey960)
Tested-by: Jerome Forissier <jerome@forissier.org> (vexpress-qemu_armv8a)
Tested-by: Jerome Forissier <jerome@forissier.org> (vexpress-qemu_virt)
Tested-by: Joakim Bech <joakim.bech@linaro.org> (RPi3B)
Tested-by: Ricardo Salveti <ricardo@foundries.io> (ZynqMP)
Tested-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> (imx-mx6qsabrelite barebox kernel 5.14.9)
Tested-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> (imx-mx6ulccimx6ulsbcpro barebox kernel 5.14.9)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1012A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1028A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1043A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1046A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1088A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS2088A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LX2160A-RDB)
Tested-by: Sumit Garg <sumit.garg@linaro.org> (Developerbox)
Tested-by: Victor Chong <victor.chong@linaro.org> (QEMUv8 AOSP)
Tested-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> (rcar-salvator_m3_2x4g / virt)
Tested-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> (rcar-salvator_m3_2x4g)
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> (bpi0)
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> (mx8mm_cl_iot_gate)
show more ...
|
| 0e6830ba | 25-Sep-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: move debug info and CC optimization level to config.mk
Move configuration switches CFG_DEBUG_INFO and CFG_CC_OPT_LEVEL
default values from arm.mk to config.mk and add a short description.
Sig
core: move debug info and CC optimization level to config.mk
Move configuration switches CFG_DEBUG_INFO and CFG_CC_OPT_LEVEL
default values from arm.mk to config.mk and add a short description.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 88876632 | 01-Oct-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: new config switch CFG_PREALLOC_RPC_CACHE
CFG_PREALLOC_RPC_CACHE=y enables preallocation of an RPC shared memory
reference per secure thread. It is default enabled for backward
configuration co
core: new config switch CFG_PREALLOC_RPC_CACHE
CFG_PREALLOC_RPC_CACHE=y enables preallocation of an RPC shared memory
reference per secure thread. It is default enabled for backward
configuration compatibility.
Disabling CFG_PREALLOC_RPC_CACHE can be useful when CFG_WITH_PAGER=y
and the pager page pool is somewhat small as RPC cache shm consumes
several kByte of unpaged memory.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
show more ...
|
| 57e642f1 | 15-Sep-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: enable system PTA upon user TA support
Ensure CFG_SYSTEM_PTA is disabled when CFG_WITH_USER_TA is disabled since
system PTA is designed to provide user TA extended system features.
Without thi
core: enable system PTA upon user TA support
Ensure CFG_SYSTEM_PTA is disabled when CFG_WITH_USER_TA is disabled since
system PTA is designed to provide user TA extended system features.
Without this change, building with CFG_SYSTEM_PTA=y and CFG_WITH_USER_TA=n
may fails for error trace like:
core/pta/system.c:227: undefined reference to `ldelf_dlopen'
core/pta/system.c:260: undefined reference to `ldelf_dlsym'
Also fix reference to the GPD TEE Internal Core API in CFG_SYSTEM_PTA
description.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| c4544143 | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
core: dt: add option to generate DTB overlay at boot
When using a memory persistent across reboots for external dtb overlay
(DRAM for instance) OP-TEE will reuse the existing dtb overlay if
CFG_EXTE
core: dt: add option to generate DTB overlay at boot
When using a memory persistent across reboots for external dtb overlay
(DRAM for instance) OP-TEE will reuse the existing dtb overlay if
CFG_EXTERNAL_DTB_OVERLAY is used. This will result in a big overlay
with duplicated nodes. In order to allow having a fresh DTB overlay
at boot, add CFG_GENERATE_DTB_OVERLAY to generate the DTB overlay at
OP-TEE boot time.
Both CFG_GENERATE_DTB_OVERLAY and CFG_EXTERNAL_DTB_OVERLAY will now
consider using the dtb address provided in r2 as well as CFG_DT_ADDR
to create the overlay if not existing.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 39ef71af | 03-Sep-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
mk: fix test on gprof and shared libs configuration for TAs
Change test for when both CFG_TA_GPROF_SUPPORT and CFG_ULIBS_SHARED
are enabled to be more strict on switches expected value. This change
mk: fix test on gprof and shared libs configuration for TAs
Change test for when both CFG_TA_GPROF_SUPPORT and CFG_ULIBS_SHARED
are enabled to be more strict on switches expected value. This change
better handles cases where, for examples, CFG_GENERATE_DTB_OVERLAY
is not defined and is malformed CFG_EXTERNAL_DTB_OVERLAY=yy. In such
case we expect both switch to be disabled and build should not fail
with error message:
"CFG_EXTERNAL_DTB_OVERLAY and CFG_GENERATE_DTB_OVERLAY are exclusive"
Reported-by: Clement Leger <clement.leger@bootlin.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
show more ...
|
| 48ca43e8 | 31-Aug-2021 |
Jerome Forissier <jerome@forissier.org> |
core: improve version string shown at boot time when not using Git
When OP-TEE is built outside of a Git repository, the implementation
version is shown as "Unknown" at boot time. For example:
I/T
core: improve version string shown at boot time when not using Git
When OP-TEE is built outside of a Git repository, the implementation
version is shown as "Unknown" at boot time. For example:
I/TC: OP-TEE version: Unknown (gcc version 10.2.1 ...
Improve this a bit by appending the major/minor revision of OP-TEE,
which is hardcoded in mk/config.mk and thus always available.
The above example becomes:
I/TC: OP-TEE version: Unknown_3.14 (gcc version 10.2.1 ...
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 06bc8d19 | 25-Aug-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
ta: pkcs11: move default config to ta sub.mk
Move PKCS#11 TA default configuration settings from mk/config.mk
to ta/pkcs11/sub.mk.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Revi
ta: pkcs11: move default config to ta sub.mk
Move PKCS#11 TA default configuration settings from mk/config.mk
to ta/pkcs11/sub.mk.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
show more ...
|
| 05ee04a8 | 05-Aug-2021 |
Jelle Sels <jelle.sels@arm.com> |
Build: Fix CFG_EMBEDDED_TS dependency
Set CFG_EMBEDDED_TS when CFG_EARLY_TA or CFG_SECURE_PARTITION
is set even when no early_ta's or SPs are added to the system.
Fixes the following error:
$ mak
Build: Fix CFG_EMBEDDED_TS dependency
Set CFG_EMBEDDED_TS when CFG_EARLY_TA or CFG_SECURE_PARTITION
is set even when no early_ta's or SPs are added to the system.
Fixes the following error:
$ make -s CFG_EARLY_TA=y
arm-linux-gnueabihf-ld.bfd: out/arm-plat-vexpress/core/kernel/early_ta.o: in function `early_ta_open':
/home/.../optee_os/core/kernel/early_ta.c:32: undefined reference to `emb_ts_open'
arm-linux-gnueabihf-ld.bfd: out/arm-plat-vexpress/core/kernel/early_ta.o:(.scattered_array_ta_stores_1_2+0x8): undefined reference to `emb_ts_get_size'
arm-linux-gnueabihf-ld.bfd: out/arm-plat-vexpress/core/kernel/early_ta.o:(.scattered_array_ta_stores_1_2+0xc): undefined reference to `emb_ts_get_tag'
arm-linux-gnueabihf-ld.bfd: out/arm-plat-vexpress/core/kernel/early_ta.o:(.scattered_array_ta_stores_1_2+0x10): undefined reference to `emb_ts_read'
arm-linux-gnueabihf-ld.bfd: out/arm-plat-vexpress/core/kernel/early_ta.o:(.scattered_array_ta_stores_1_2+0x14): undefined reference to `emb_ts_close'
make: *** [core/arch/arm/kernel/link.mk:45: out/arm-plat-vexpress/core/all_objs.o] Error 1
Github issue:
https://github.com/OP-TEE/optee_os/issues/4729#issuecomment-893308216
Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
show more ...
|
| df7e4e96 | 09-Jul-2021 |
Jerome Forissier <jerome@forissier.org> |
Update revision for release tag 3.14.0-rc1
Signed-off-by: Jerome Forissier <jerome@forissier.org> |
| 300faa62 | 30-Apr-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: REE FS: introduce CFG_REE_FS_ALLOW_RESET
New boolean configuration switch CFG_REE_FS_ALLOW_RESET that, when
enabled, will make OP-TEE OS to allow REE FS content to be reset in
the Linux filesy
core: REE FS: introduce CFG_REE_FS_ALLOW_RESET
New boolean configuration switch CFG_REE_FS_ALLOW_RESET that, when
enabled, will make OP-TEE OS to allow REE FS content to be reset in
the Linux filesystem even when RPMB FS is enabled and already stores a
REE FS rollback protection hash. This switch is intended to test purpose
where REE FS can be wiped because the device flash memory was programmed
with brand new build artifacts.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
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| f2dad489 | 21-May-2021 |
Sergiy Kibrik <Sergiy_Kibrik@epam.com> |
core: pta: add generic RNG pseudo TA
Platforms that include hardware-based RNGs and implement
hw_get_random_byte() may benefit from already implemented bus framework
and rng driver [1].
For this rea
core: pta: add generic RNG pseudo TA
Platforms that include hardware-based RNGs and implement
hw_get_random_byte() may benefit from already implemented bus framework
and rng driver [1].
For this reason the interface of rng.pta implemented for Developerbox
platform is re-used. Interface is generic and corresponds to in-kernel
optee-rng driver.
Pseudo TA interface is specifically used so that credible entropy is
available to REE early at boot, even before user-space is fully up.
[1] https://lwn.net/Articles/777260/
Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 8443e88e | 29-Apr-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
config: add description for CFG_RPMB_* config switches
Add a short description for some CFG_RPMB_* configuration switches
not described anywhere.
Signed-off-by: Etienne Carriere <etienne.carriere@l
config: add description for CFG_RPMB_* config switches
Add a short description for some CFG_RPMB_* configuration switches
not described anywhere.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 30c13f9e | 30-Apr-2021 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
Update CHANGELOG.md for 3.13.0
Update CHANGELOG for 3.13.0 and collect Tested-by tags.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6d
Update CHANGELOG.md for 3.13.0
Update CHANGELOG for 3.13.0 and collect Tested-by tags.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6dlsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6dlsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6qpsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6sllevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6ulevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6ullevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx6ulzevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx7dsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx7ulpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx8mmevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx8mnevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx8mqevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx8qmmek)
Tested-by: Clement Faure <clement.faure@nxp.com> (mx8qxpmek)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-ev1/dk2 gp pkcs11)
Tested-by: Igor Opaniuk <igor.opaniuk@foundries.io> (Poplar)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (imx-mx8mqevk)
Tested-by: Jerome Forissier <jerome@forissier.org> (HiKey GP PKCS#11)
Tested-by: Jerome Forissier <jerome@forissier.org> (HiKey960 GP PKCS#11)
Tested-by: Jerome Forissier <jerome@forissier.org> (QEMU GP PKCS#11)
Tested-by: Jerome Forissier <jerome@forissier.org> (QEMUv8 GP PKCS#11)
Tested-by: Joakim Bech <joakim.bech@linaro.org> (RPi3B)
Tested-by: Ricardo Salveti <ricardo@foundries.io> (ZynqMP)
Tested-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> (ccimx6ulsbcpro barebox upstream kernel)
Tested-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> (imx6qsabrelite barebox upstream kernel)
Tested-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> (RCAR M3)
Tested-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> (RCAR M3/virtualization)
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