| 8e74d476 | 09-Jan-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
Update CHANGELOG for 3.20.0
Update CHANGELOG for 3.20.0 and collect Tested-by tags.
Tested-by: Johann Neuhauser <jneuhauser@dh-electronics.com> (stm32mp1-157A_DHCOR_AVENGER96) Tested-by: Johann Neu
Update CHANGELOG for 3.20.0
Update CHANGELOG for 3.20.0 and collect Tested-by tags.
Tested-by: Johann Neuhauser <jneuhauser@dh-electronics.com> (stm32mp1-157A_DHCOR_AVENGER96) Tested-by: Johann Neuhauser <jneuhauser@dh-electronics.com> (stm32mp1-157C_DHCOM_PDK2) Tested-by: Joakim Bech <joakim.bech@linaro.org> (RPi3) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (imx-mx8mqevk) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (RockPi4) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_virt) Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_DK2) Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_EV1) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qsabresd) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sllevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sxsabresd) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ullevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulzevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7dsabresd) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7ulpevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mmevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mnevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mqevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mpevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qmmek) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qxpmek) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8ulpevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx93evk) Tested-by: Ricardo Salveti <ricardo@foundries.io> (k3-am64x) Tested-by: Ricardo Salveti <ricardo@foundries.io> (ZynqMP) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 4c4212e9 | 25-Feb-2021 |
Vincent Guittot <vincent.guittot@linaro.org> |
core: lib: scmi-server: Build a SCMI server from SCP-firmware
Adds build of an SCMI server library using SCP-firmware source tree upon boolean configuration switch CFG_SCMI_SCPFW. Platform must set
core: lib: scmi-server: Build a SCMI server from SCP-firmware
Adds build of an SCMI server library using SCP-firmware source tree upon boolean configuration switch CFG_SCMI_SCPFW. Platform must set the SCP firmware target product with CFG_SCMI_SCPFW_PRODUCT and the root path of the SCP-firmware source tree with CFG_SCP_FIRMWARE.
CFG_SCMI_SCPFW and CFG_SCMI_MSG_DRIVERS are exclusives alternate implementations of SCMI services. The former implements almost all the SCMI specification while the later implements only basic SCMI services.
SCP-firmware is configured with CMake as an external project to generate the embedded module resource source and header files to be built with SCP-firmware.
This commit integrates the 2 SCP-firmware products designed for OP-TEE in SCP-firmware source tree. Product optee-fvp targets platform vexpress flavors FVP and Qemus. Product optee-stm32mp1 targets platform stm32mp1.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 16a5030f | 02-Dec-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: pta: scmi: internal switches for supported transports
Adds internal configuration switch _CFG_SMCI_PTA_SMT_HEADER and _CFG_SCMI_PTA_MSG_HEADER to specify which are supported. This change will
core: pta: scmi: internal switches for supported transports
Adds internal configuration switch _CFG_SMCI_PTA_SMT_HEADER and _CFG_SCMI_PTA_MSG_HEADER to specify which are supported. This change will ease integration of the alternate SCMI server build from SCP-firmware.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 8bbc2e9c | 29-Nov-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
Update reported version to GP Core Internal API v1.3.1
Updates the reported version to 1.3.1. Three new defines: - TEE_CORE_API_REQUIRED_MAJOR_VERSION - TEE_CORE_API_REQUIRED_MINOR_VERSION - TEE_COR
Update reported version to GP Core Internal API v1.3.1
Updates the reported version to 1.3.1. Three new defines: - TEE_CORE_API_REQUIRED_MAJOR_VERSION - TEE_CORE_API_REQUIRED_MINOR_VERSION - TEE_CORE_API_REQUIRED_MAINTENANCE_VERSION are added by the standard as a way for the TA to specify required version of the API. OP-TEE only supports downgrading to version 1.1.
A simplified OP-TEE specific method is also provided: Adds the configuration option CFG_TA_OPTEE_CORE_API_COMPAT_1_1 which enables TEE Internal Core API v1.1 compatibility for in-tree TAs.
The TA dev kit is also updated to recognize CFG_TA_OPTEE_CORE_API_COMPAT_1_1 and set define __OPTEE_CORE_API_COMPAT_1_1 to 1 if set.
These new defines does not do anything yet, but in following commits functions and types will be updated gradually until all functions and types changed in version 1.3.1 compared to the ones in v1.1 have been updated.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 45507d10 | 18-Nov-2022 |
Khoa Hoang <admin@khoahoang.com> |
Add support for compiler stack protector
This change add support for CFG_CORE_STACK_PROTECTOR{,_STRONG,_ALL} and CFG_TA_STACK_PROTECTOR{,_STRONG,_ALL}. This flag enable the compiler stack overflow p
Add support for compiler stack protector
This change add support for CFG_CORE_STACK_PROTECTOR{,_STRONG,_ALL} and CFG_TA_STACK_PROTECTOR{,_STRONG,_ALL}. This flag enable the compiler stack overflow protection feature -fstack-protector* and also generate random stack canary value on kernel boot and TA entry.
Weak function plat_get_random_stack_canary() can be override by platform to provide random stack canary value for the core kernel.
Signed-off-by: Khoa Hoang <admin@khoahoang.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 7e75ca54 | 01-Apr-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
Basic fault mitigation routines
Adds basic fault mitigation routines designed to help protecting from fault injection attacks on the hardware. This is by no means bullet proof, but it should at leas
Basic fault mitigation routines
Adds basic fault mitigation routines designed to help protecting from fault injection attacks on the hardware. This is by no means bullet proof, but it should at least improve the situation.
These routines focus on verifying that a function has been called and that the returned value matches the result from the function. This is done by having a handshake between the caller and the callee where also the return value is transmitted in a separate channel.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 1dc8870c | 23-Nov-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
mk: compile with -std=gnu11 instead of -std=gnu99
Changes C source build directives to comply with C11 instead of C99. This change affects core and user applications and libraries. C11 is supported
mk: compile with -std=gnu11 instead of -std=gnu99
Changes C source build directives to comply with C11 instead of C99. This change affects core and user applications and libraries. C11 is supported in GCC since version 4.7, see [1].
This change is initially intended to bring aligned_alloc() support in OP-TEE.
Link: [1] https://gcc.gnu.org/wiki/C11Status Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| cb94c145 | 21-Oct-2022 |
Weizhao Jiang <weizhaoj@amazon.com> |
core: implement a method to dump user TA runtime status
This patch is to dump user TA runtime status for debug purposes. The change includes: 1. Add new command (STATS_CMD_TA_STATS) in the stats PTA
core: implement a method to dump user TA runtime status
This patch is to dump user TA runtime status for debug purposes. The change includes: 1. Add new command (STATS_CMD_TA_STATS) in the stats PTA. 2. Add tee_ta_dump_stats() to scan all ongoing TA instance and sessions and snapshot their status. 3. Add new function: entry_dump_memstats() to __utee_entry() to get TA heap statistics. 4. Add new compile option (CFG_TA_STATS, default n) to enable this feature.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Tested-by: Weizhao Jiang <weizhaoj@amazon.com> Signed-off-by: Weizhao Jiang <weizhaoj@amazon.com> [jf: edit commit message] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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| c34d0d91 | 05-Sep-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: support loading TAs signed with a subkey
Adds support to load TAs signed with subkey or a chain of subkeys. This allows delegation of TA signing without distributing the root key. TAs signed w
core: support loading TAs signed with a subkey
Adds support to load TAs signed with subkey or a chain of subkeys. This allows delegation of TA signing without distributing the root key. TAs signed with a subkey are confined to the UUID-V5 namespace of the subkey to avoid TA UUID clashes with different subkeys.
SHDR_SUBKEY is a type of header which enables chains of public keys. The public root key is used to verify the first public subkey, which then is used to verify the next public subkey and so on.
The TA is finally verified using the last subkey. All these headers are added in front of the TA binary so everything needed to verify the TA is available when it's loaded into memory.
For example: Subkey struct shdr magic: 0x4f545348 img_type: 3 (SHDR_SUBKEY) img_size: 320 bytes algo: 0x70414930 (TEE_ALG_RSASSA_PKCS1_PSS_MGF1_SHA256) hash_size: 32 bytes sig_size: 256 bytes hash: f573f329fe77be686ce71647909c4ea35b5e1cd7de86369bd7d9fca31f6a4d65 struct shdr_subkey uuid: f04fa996-148a-453c-b037-1dcfbad120a6 name_size: 64 subkey_version: 1 max_depth: 4 algo: 0x70414930 (TEE_ALG_RSASSA_PKCS1_PSS_MGF1_SHA256) attr_count: 2 next name: "mid_level_subkey" Next header at offset: 692 (0x2b4) Subkey struct shdr magic: 0x4f545348 img_type: 3 (SHDR_SUBKEY) img_size: 320 bytes algo: 0x70414930 (TEE_ALG_RSASSA_PKCS1_PSS_MGF1_SHA256) hash_size: 32 bytes sig_size: 256 bytes hash: 233a6dcf1a2cf69e50cde8e20c4129157da707c76fa86ce12ee31037edef02d7 struct shdr_subkey uuid: 1a5948c5-1aa0-518c-86f4-be6f6a057b16 name_size: 64 subkey_version: 1 max_depth: 3 algo: 0x70414930 (TEE_ALG_RSASSA_PKCS1_PSS_MGF1_SHA256) attr_count: 2 next name: "subkey1_ta" Next header at offset: 1384 (0x568) Bootstrap TA struct shdr magic: 0x4f545348 img_type: 1 (SHDR_BOOTSTRAP_TA) img_size: 84576 bytes algo: 0x70414930 (TEE_ALG_RSASSA_PKCS1_PSS_MGF1_SHA256) hash_size: 32 bytes sig_size: 256 bytes hash: ea31ac7dc2cc06a9dc2853cd791dd00f784b5edc062ecfa274deeb66589b4ca5 struct shdr_bootstrap_ta uuid: 5c206987-16a3-59cc-ab0f-64b9cfc9e758 ta_version: 0 TA offset: 1712 (0x6b0) bytes TA size: 84576 (0x14a60) bytes
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_virt) Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| afacf356 | 23-Sep-2022 |
Jerome Forissier <jerome.forissier@linaro.org> |
Update CHANGELOG for 3.19.0
Update CHANGELOG for 3.19.0 and collect Tested-by tags.
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd) Tested-by: Clement Faure <clement.faure@nxp.c
Update CHANGELOG for 3.19.0
Update CHANGELOG for 3.19.0 and collect Tested-by tags.
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qsabresd) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sllevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sxsabresd) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ullevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulzevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7dsabresd) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7ulpevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mmevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mnevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mqevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mpevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qmmek) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qxpmek) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8dxlevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8ulpevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx93evk) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a, GP, PKCS#11) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_virt, GP, PKCS#11) Tested-by: Manorit Chawdhry <m-chawdhry@ti.com> (k3-j721e) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1012A-RDB) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1028A-RDB) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1088A-RDB) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS2088A-RDB) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1046A-RDB) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1043A-RDB) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LX2160A-RDB) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LX2160A-QDS) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (hikey-hikey, GP, PKCS#11) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (imx-mx8mqevk) Tested-by: Igor Opaniuk <igor.opaniuk@foundries.io> (Poplar) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP) Tested-by: Balint Dobszay <balint.dobszay@arm.com> (fvp-ts) Tested-by: Ricardo Salveti <ricardo@foundries.io> (imx-mx8mmevk, plug-and-trust v0.4.0) Tested-by: Ricardo Salveti <ricardo@foundries.io> (ZynqMP, GP, PKCS#11) Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_DK2, gp, pkcs11) Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_EV1, gp, pkcs11) Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 7c2317a7 | 26-Sep-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
core: boot: do not force implement the external device-tree ABI
Do not implement external device tree ABI if CFG_EXTERNAL_DT=n. Some ecosystem implementation do not require OP-TEE to modify or use t
core: boot: do not force implement the external device-tree ABI
Do not implement external device tree ABI if CFG_EXTERNAL_DT=n. Some ecosystem implementation do not require OP-TEE to modify or use this external device tree. This change is useful on 32bits systems where OP-TEE only needs to pass BL33 DTB base address provided by earlier boot stage: TF-A BL2.
CFG_EXTERNAL_DT default value is defined by CFG_DT for backward compatibility of OP-TEE default configuration.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| bfdeae23 | 23-Jun-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: pgt: support preallocated translation tables for S-EL0
With CFG_CORE_PREALLOC_EL0_TBLS=y translation tables are allocated for a user space context at the time when the mapping is added a struc
core: pgt: support preallocated translation tables for S-EL0
With CFG_CORE_PREALLOC_EL0_TBLS=y translation tables are allocated for a user space context at the time when the mapping is added a struct vm_region. The translation tables will be kept available for the S-EL0 context as long at the mappings are unchanged.
Secure Partitions (SPs) can depend on translation tables always being available and avoid having to wait for translation tables.
Memory for the translation tables is allocated from the same memory as used for TAs and SPs. The number of available translation tables are limited by the amount of TA/SP memory available.
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 93dc6b29 | 23-Sep-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add pointer authentication support
Previously pointer authentication was only supported for TAs. With this patch add a configuration option CFG_CORE_PAUTH to enable support for core. Each priv
core: add pointer authentication support
Previously pointer authentication was only supported for TAs. With this patch add a configuration option CFG_CORE_PAUTH to enable support for core. Each privileged thread has its own APIA key. There are also a separate APIA key for each physical core used when handling an abort or when using the tmp stack.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 1fdb1c4f | 05-Sep-2022 |
Jelle Sels <jelle.sels@arm.com> |
ffa: Export ffa.h to be used by host
The ffa.h file is needed by the OP-TEE test suite. Export it so it can be used by it.
Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jerome Forissier
ffa: Export ffa.h to be used by host
The ffa.h file is needed by the OP-TEE test suite. Export it so it can be used by it.
Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 71f2c921 | 16-Aug-2022 |
Jerome Forissier <jerome.forissier@linaro.org> |
clang.mk: fix build on AArch64 host
When building on an AArch64 host and using OP-TEE's build.git [1], the AArch64 cross compiler prefix is "aarch64-linux-" instead of the usual "aarch64-linux-gnu-"
clang.mk: fix build on AArch64 host
When building on an AArch64 host and using OP-TEE's build.git [1], the AArch64 cross compiler prefix is "aarch64-linux-" instead of the usual "aarch64-linux-gnu-". This happens due to [2]. Clang still expects --target=aarch64-linux-gnu so for convenience map the prefix accordingly in mk/clang.mk.
Link: [1] https://github.com/OP-TEE/build.git Link: [2] https://github.com/OP-TEE/build/blob/3.18.0/toolchain.mk#L97 Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| f5411aaf | 17-Aug-2022 |
Judy Wang <wangjudy@microsoft.com> |
core: add CFG_REE_FS_INTEGRITY_RPMB for roll-back protection of REE
If we enable CFG_RPMB_FS and CFG_REE_FS at the same time in optee-os, with tee-supplicant only supports REE, calls from xtest to
core: add CFG_REE_FS_INTEGRITY_RPMB for roll-back protection of REE
If we enable CFG_RPMB_FS and CFG_REE_FS at the same time in optee-os, with tee-supplicant only supports REE, calls from xtest to ree_fs_open() will attempt to access RPMB for roll-back protection, which will fail because tee-supplicant can't access RPMB.
In some platforms, we only want optee-os to support RPMB key provision checking by invoking any RPMB read/writes, but don't care about whether contents could be read/written. The tee-supplicant in these platform is limited to REE only, because there's an existing issue in Linux OS causing kernel drivers failed to support RPMB. So we need an option to prevent applications like xtest to access RPMB when calling ree_fs_open(), but keep the ability to call RPMB fs related apis. When we check the key thru RPMB read. If key is provisioned, tee-supplicant will return TEEC_ERROR_ITEM_NOT_FOUND. If not, optee-os will return TEE_ERROR_STORAGE_NOT_AVAILABLE.
How-tested: execute `xtest -t regression` with optee-os CFG_REE_FS=y and CFG_RPMB_FS=y. optee-client RPMB_EMU=n Many testcases will fail. (ex: case 1004)
Signed-off-by: Judy Wang <wangjudy@microsoft.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 391a3854 | 29-Apr-2022 |
Andrew Davis <afd@ti.com> |
core: Add hw_get_random_bytes()
Currently there are two options for supporting hardware RNG, implementing hw_get_random_byte() or overriding crypto_rng_read().
crypto_rng_read() is provided by eith
core: Add hw_get_random_bytes()
Currently there are two options for supporting hardware RNG, implementing hw_get_random_byte() or overriding crypto_rng_read().
crypto_rng_read() is provided by either a software PRNG or by a hardware RNG through a weak function in rng_hw.c. This weak function repeatedly calls hw_get_random_byte(). This can be an unneeded slowdown for platforms that fetch more than one byte of randomness per call to their HW RNG (all of them). The usual pattern is to store these extra bytes in a FIFO and feed them out one at a time. But since the only two callers of hw_get_random_byte() are themselves users of more than one byte this indirection is unnecessary. To get around this some platforms have also started overriding crypto_rng_read() which makes the API flow a bit less intuitive than it could be.
Plan here is that platforms only need to implement hw_get_random_bytes(). This can be called with length = 1 if we only need a single byte. But in the more common case we get a performance boost and simplify the RNG call flow.
To start we keep hw_get_random_byte() and have the new hw_get_random_bytes() use it to get platform HW RNG byte at a time. When we finish moving all plats over to hw_get_random_bytes() then hw_get_random_byte() can be removed.
Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 1ee64703 | 23-Jun-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
Update CHANGELOG for 3.18.0
Update CHANGELOG for 3.18.0 and collect Tested-by tags.
Tested-by: Igor Opaniuk <igor.opaniuk@foundries.io> (Poplar) Tested-by: Jerome Forissier <jerome.forissier@linaro
Update CHANGELOG for 3.18.0
Update CHANGELOG for 3.18.0 and collect Tested-by tags.
Tested-by: Igor Opaniuk <igor.opaniuk@foundries.io> (Poplar) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_virt, GP, PKCS#11) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP Base RevC) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP Foundation model) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (imx-mx8mqevk) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a, GP, PKCS#11) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (hikey-hikey960, GP, PKCS#11) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (hikey-hikey, GP, PKCS#11) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qsabresd) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sllevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sxsabresd) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ullevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulzevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7dsabresd) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7ulpevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mmevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mnevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mqevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mpevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qmmek) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qxpmek) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8dxlevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8ulpevk) Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1, gp, pkcs11, stmm) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1012A-RDB) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1028A-RDB) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1088A-RDB) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS2088A-RDB) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1046A-RDB) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1043A-RDB) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LX2160A-RDB) Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LX2160A-QDS) Tested-by: Ricardo Salveti <ricardo@foundries.io> (ZynqMP) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| c36d2192 | 09-May-2022 |
Balint Dobszay <balint.dobszay@arm.com> |
core: sp: handle memory regions w/o base address
The FF-A spec states that in the SP manifest a base address is not mandatory for memory regions. If the field is not present, the specified memory re
core: sp: handle memory regions w/o base address
The FF-A spec states that in the SP manifest a base address is not mandatory for memory regions. If the field is not present, the specified memory region must be allocated by the SPMC and mapped to the SP's context.
A copy of the SP manifest fdt is used for passing the memory region virtual addresses to the SP. Additional space is allocated when copying the fdt so the originally not present base address fields can be added later.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> [jf: edit description to avoid checkpatch spelling warning] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 916cc52a | 29-Apr-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
drivers: scmi-msg: add SCMI MSG message protocol
Implements MSG header protocol to handle SCMI messages. MSG header protocol was introduced in Linux kernel v5.15 [1]. It relies on normal cached shar
drivers: scmi-msg: add SCMI MSG message protocol
Implements MSG header protocol to handle SCMI messages. MSG header protocol was introduced in Linux kernel v5.15 [1]. It relies on normal cached shared memory buffer using a 32bit header followed by the SCMI message payload.
To support this message interface, the SCMI PTA defines a new capability and a new command. Capability PTA_SCMI_CAPS_MSG_HEADER allows client and service to negotiate the desired transport configuration. Command PTA_SCMI_CMD_PROCESS_MSG_CHANNEL allows client to request processing of a message sent based on that message exchange protocol.
Platforms shall enable configuration switch CFG_SCMI_MSG_SHM_MSG to have their SCMI service supporting that communication protocol.
Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f301bba0ca7392d16a6ea4f1d264a91f1fadea1a Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 435c1273 | 16-May-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
mk: config.mk: fix dependency on CFG_SCMI_MSG_SHM_MSG
Fixes inaccurate test on CFG_SC MI_MSG_SHM_MSG config switch that is not yet defined. Before this fix was CFG_SCMI_MSG_SMT_THREAD_ENTRY always f
mk: config.mk: fix dependency on CFG_SCMI_MSG_SHM_MSG
Fixes inaccurate test on CFG_SC MI_MSG_SHM_MSG config switch that is not yet defined. Before this fix was CFG_SCMI_MSG_SMT_THREAD_ENTRY always forced to n.
Fixes: 28e51326a5c9 ("mk: config.mk: describe and initialize CFG_SCMI_MSG_*_ENTRY switches") Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 28e51326 | 29-Apr-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
mk: config.mk: describe and initialize CFG_SCMI_MSG_*_ENTRY switches
Describe and set a default value to existing CFG_SCMI_MSG_*_ENTRY configuration switches that allow to optimize memory which is d
mk: config.mk: describe and initialize CFG_SCMI_MSG_*_ENTRY switches
Describe and set a default value to existing CFG_SCMI_MSG_*_ENTRY configuration switches that allow to optimize memory which is desired when enabling pager and interrupt or fastcall SMC entry for SCMI channels.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 3bfa418b | 13-May-2022 |
Jerome Forissier <jerome.forissier@linaro.org> |
build: introduce CFG_OPTEE_REVISION_EXTRA
Adds CFG_OPTEE_REVISION_EXTRA (default: empty) which can be used to append a custom string to the revision string shown in the boot banner. A typical use ca
build: introduce CFG_OPTEE_REVISION_EXTRA
Adds CFG_OPTEE_REVISION_EXTRA (default: empty) which can be used to append a custom string to the revision string shown in the boot banner. A typical use case is build environments such as Yocto/OpenEmbedded which check out a particular version of the optee_os repository and may add patches on top. In this case the revision string is something like:
3.17.0-dev (gcc version ...
which doesn't give any information on what modifications are added and therefore makes it difficult to know for sure if a deployed binary is indeed the expected one (even more so when the build date is fixed via SOURCE_DATE_EPOCH for reproducible builds). CFG_OPTEE_REVISION_EXTRA allows to append a specific build identifier. For example:
$ make CFG_OPTEE_REVISION_EXTRA=-mybuild_1234
would give:
3.17.0-dev-mybuild_1234
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 2e1b85fe | 04-Apr-2022 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
tpm2: Add TPM2 as PCR provider to TCG eventlog parsing framework
TCG eventlog parsing framework parses the eventlog and extends the PCR's. For this, it needs a provider for PCR's. Register TPM2 as a
tpm2: Add TPM2 as PCR provider to TCG eventlog parsing framework
TCG eventlog parsing framework parses the eventlog and extends the PCR's. For this, it needs a provider for PCR's. Register TPM2 as a provider to this framework.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 001524d4 | 06-May-2022 |
Jerome Forissier <jerome.forissier@linaro.org> |
build: allow multiple occurrences of the same directory in subdirs-y
This change enables adding the same directory several times to subdirs-y in sub.mk without causing warnings. This means we can no
build: allow multiple occurrences of the same directory in subdirs-y
This change enables adding the same directory several times to subdirs-y in sub.mk without causing warnings. This means we can now use patterns such as:
subdirs-$(CFG_FOO) += foobar subdirs-$(CFG_BAR) += foobar
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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