dt-bindings: add stm32 TAMP support

Add device tree bindings for the TAMP hardware block stm32mpxx
platforms. These bindings permit the description of the configuration
of tamper events.

Signed-off

dt-bindings: add stm32 TAMP support

Add device tree bindings for the TAMP hardware block stm32mpxx
platforms. These bindings permit the description of the configuration
of tamper events.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: stm32_rtc: add time stamping feature support

Support the time stamping features of the RTC. It is useful to generate
a timestamp whenever a particular event occurs.

Signed-off-by: Gatien C

drivers: stm32_rtc: add time stamping feature support

Support the time stamping features of the RTC. It is useful to generate
a timestamp whenever a particular event occurs.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: stm32_gpio: add stm32_gpio_get_bank_id() helper

Add stm32_gpio_get_bank_id() helper function to get the STM32
GPIO bank ID related to its GPIO chip

Signed-off-by: Gatien Chevallier <gatien

drivers: stm32_gpio: add stm32_gpio_get_bank_id() helper

Add stm32_gpio_get_bank_id() helper function to get the STM32
GPIO bank ID related to its GPIO chip

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: interrupt: add set_wake for power-management wake-on on interrupt

For interrupt controllers that can handle power-management wake-up
when receiving an interrupt, add the operation set_wake().

core: interrupt: add set_wake for power-management wake-on on interrupt

For interrupt controllers that can handle power-management wake-up
when receiving an interrupt, add the operation set_wake().

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: kernel: dt_driver: fix copy/paste comment

While adding DT_DRIVER_PINCTRL, an incorrect word was reported by
copy/paste from the existing comment for DT_DRIVER_RSTCTRL.

Drop the word 'reset' f

core: kernel: dt_driver: fix copy/paste comment

While adding DT_DRIVER_PINCTRL, an incorrect word was reported by
copy/paste from the existing comment for DT_DRIVER_RSTCTRL.

Drop the word 'reset' from the comment for DT_DRIVER_PINCTRL.

Fixes: b5aff6de7052 ("core: dt_driver: add support for DT_DRIVER_PINCTRL")
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

dt-bindings: align RIMU documentation with STM32MP21

Update RIF_CIDSEL_P and RIF_CIDSEL_M defines to be align with STM32MP21.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-b

dt-bindings: align RIMU documentation with STM32MP21

Update RIF_CIDSEL_P and RIF_CIDSEL_M defines to be align with STM32MP21.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

dt-bindings: add STM32MP21x shared bindings

Adds STM32MP21x SoC family bindings that share STM32MP25
RISAF bindings.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by:

dt-bindings: add STM32MP21x shared bindings

Adds STM32MP21x SoC family bindings that share STM32MP25
RISAF bindings.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

dt-bindings: add STM32MP21 RIFSC bindings

Add STM32MP21 specific RIFSC bindings.

Co-developed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevalli

dt-bindings: add STM32MP21 RIFSC bindings

Add STM32MP21 specific RIFSC bindings.

Co-developed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: boot_mem: enable asan support

Add boot_mem_init_asan() to tag all allocated memory with
asan_tag_access().

Allocations with boot_mem_alloc() and boot_mem_alloc_tmp() are tagged
with asan_tag_

core: boot_mem: enable asan support

Add boot_mem_init_asan() to tag all allocated memory with
asan_tag_access().

Allocations with boot_mem_alloc() and boot_mem_alloc_tmp() are tagged
with asan_tag_access().

boot_mem_foreach_padding() temporarily allow access to paddings for the
callback and restores no-access if the callback returns false to tell
that the padding wasn't consumed.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: replace CFG_DYN_STACK_CONFIG with CFG_DYN_CONFIG

This commit replaces CFG_DYN_STACK_CONFIG with CFG_DYN_CONFIG since now
RISC-V also supports CFG_DYN_STACK_CONFIG.

Signed-off-by: Alvin Chang

core: replace CFG_DYN_STACK_CONFIG with CFG_DYN_CONFIG

This commit replaces CFG_DYN_STACK_CONFIG with CFG_DYN_CONFIG since now
RISC-V also supports CFG_DYN_STACK_CONFIG.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

scmi-server: configure clock service from DT

scmi_server_scpfw can now retrieve clocks description from DT.

Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Acked-by: Jerome Forissier <je

scmi-server: configure clock service from DT

scmi_server_scpfw can now retrieve clocks description from DT.

Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

dt-bindings: update LTDC layer numbers on stm32mp2x platforms

On stm32mp2x platforms, according to the reference manual, the LTDC
layers are named L1/2/3, not L0/1/2.

Signed-off-by: Gatien Chevalli

dt-bindings: update LTDC layer numbers on stm32mp2x platforms

On stm32mp2x platforms, according to the reference manual, the LTDC
layers are named L1/2/3, not L0/1/2.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: mm: fix va to index calculation for RV64

On RV64, shifting va is not enough when top bits are
present in the virtual address, e.g. for Sv48, bits
63-48 must be set when bit 47 is set to form a

core: mm: fix va to index calculation for RV64

On RV64, shifting va is not enough when top bits are
present in the virtual address, e.g. for Sv48, bits
63-48 must be set when bit 47 is set to form a valid
virtual address.

In this case, we need to mask the base-level virtual
addresses to clear any extended bits before calculating
the index.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

show more ...

core: mm: refactor ASLR mapping for architecture support

To allow adding RISC-V ASLR support, add arch_aslr_base_addr()
which will be used to apply architecture specific ASLR base
calculation.

Sign

core: mm: refactor ASLR mapping for architecture support

To allow adding RISC-V ASLR support, add arch_aslr_base_addr()
which will be used to apply architecture specific ASLR base
calculation.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

show more ...

drivers: wdt: add implementation of SMCWD_GET_TIMELEFT

Implement watchdog SMC service SMCWD_GET_TIMELEFT that is optional
and allows non-secure world to get information on watchdog state.
The servic

drivers: wdt: add implementation of SMCWD_GET_TIMELEFT

Implement watchdog SMC service SMCWD_GET_TIMELEFT that is optional
and allows non-secure world to get information on watchdog state.
The service is supported by new watchdog driver operation handler
get_timeleft.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

drivers: stm32_iwdg: remove OTP access in driver

Now we know if the watchdog is running by reading the hardware,
there is no need to read the OTP fuses related to the watchdog.
This allows removing

drivers: stm32_iwdg: remove OTP access in driver

Now we know if the watchdog is running by reading the hardware,
there is no need to read the OTP fuses related to the watchdog.
This allows removing platform function stm32_get_iwdg_otp_config()
and consequently stm32_iwdg.h header file.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

core: kernel: Remove CFG_BOOT_INIT_CURRENT_THREAD_CORE_LOCAL

Now both ARM and RISC-V architectures support initialize
thread_core_local[current_core_pos] before calling C code. Thus, we can
deprecat

core: kernel: Remove CFG_BOOT_INIT_CURRENT_THREAD_CORE_LOCAL

Now both ARM and RISC-V architectures support initialize
thread_core_local[current_core_pos] before calling C code. Thus, we can
deprecate CFG_BOOT_INIT_CURRENT_THREAD_CORE_LOCAL and corresponding
code.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

show more ...

core: dynamic allocation of threads and their stacks

With CFG_DYN_CONFIG enabled, use dynamic allocation of threads and their
stacks.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Revie

core: dynamic allocation of threads and their stacks

With CFG_DYN_CONFIG enabled, use dynamic allocation of threads and their
stacks.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: add thread_count to thread_init_threads()

Add a thread_count parameter to thread_init_threads(). This must currently
always be equal to CFG_NUM_THREADS, but may become a dynamic configuration

core: add thread_count to thread_init_threads()

Add a thread_count parameter to thread_init_threads(). This must currently
always be equal to CFG_NUM_THREADS, but may become a dynamic configuration
parameter with CFG_DYN_CONFIG=y in later patches.

The array threads[] is changed into a pointer to allow dynamic
allocation in later patches. The assembly code is updated accordingly to
handle a pointer instead of an array.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Tested-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: mm: shared xlat tables for NEX_DYN_VASPACE

Mappings in MEM_AREA_NEX_DYN_VASPACE belong to the nexus and are must to
be the same for all partitions. Since these mappings must be updated in
the

core: mm: shared xlat tables for NEX_DYN_VASPACE

Mappings in MEM_AREA_NEX_DYN_VASPACE belong to the nexus and are must to
be the same for all partitions. Since these mappings must be updated in
the partitions after the MMU has been enabled. Partitions share
translation tables for this mappings, so we only need to update in one
translation table when adding or removing mappings.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: dynamic allocation of thread_core_local and its stacks

With CFG_DYN_CONFIG enabled, use dynamic allocation of thread_core_local
and the two stacks, tmp_stack and abt_stack, recorded in it.

Si

core: dynamic allocation of thread_core_local and its stacks

With CFG_DYN_CONFIG enabled, use dynamic allocation of thread_core_local
and the two stacks, tmp_stack and abt_stack, recorded in it.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

core: add core_count to thread_init_thread_core_local()

Add a core_count parameter to thread_init_thread_core_local() to enable
dynamic configuration of the number of supported cores when configured

core: add core_count to thread_init_thread_core_local()

Add a core_count parameter to thread_init_thread_core_local() to enable
dynamic configuration of the number of supported cores when configured
with CFG_DYN_STACK_CONFIG=y, or it must be equal to
CFG_TEE_CORE_NB_CORE. This is needed in later patches where the number
of cores is configured dynamically.

The array thread_core_local[] is changed into a pointer to allow dynamic
allocation in later patches. The assembly code is updated accordingly to
handle a pointer instead of an array.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: ffa: reserve physical memory for manifest

With CFG_CORE_SEL2_SPMC=y (Hafnium as SPMC at S-EL2), the FF-A manifest
passed to OP-TEE resides in the memory reserved for OP-TEE just before
the loa

core: ffa: reserve physical memory for manifest

With CFG_CORE_SEL2_SPMC=y (Hafnium as SPMC at S-EL2), the FF-A manifest
passed to OP-TEE resides in the memory reserved for OP-TEE just before
the load address. The physical memory pool is initialized with the entire
range of secure memory, with holes carved out for already used memory.

Temporarily allocate the physical memory used by the manifest until it's
not needed any longer and released by release_manifest_dt().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

core: drivers: support SiFive UART

Add sifive uart support.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zo

core: drivers: support SiFive UART

Add sifive uart support.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Acked-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

riscv: kernel: support booting non-contiguous non-zero-based hart IDs

Currently, OP-TEE assumes 0 <= hartid < CFG_TEE_CORE_NB_CORE,
and must be contiguous, which fails to accommodate different
CPU t

riscv: kernel: support booting non-contiguous non-zero-based hart IDs

Currently, OP-TEE assumes 0 <= hartid < CFG_TEE_CORE_NB_CORE,
and must be contiguous, which fails to accommodate different
CPU topologies. For example, some RISC-V platforms, such as
the HiFive Unmatched board, do not run Linux and OP-TEE on
hart0, as it is a monitor core without supervisor mode support.

To address this, introduce hart_index, which is used to index
per-hart structures, such as thread_core_local and root_pgt.
The hart_index will range from 0 to (CFG_TEE_CORE_NB_CORE - 1),
and the primary hart will have an index of 0.

Additionally, a new function, boot_primary_init_core_ids(),
is added to initialize secondary hart IDs for booting via
sbi_hsm_hart_start().

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

show more ...