| 80d65d27 | 20-Apr-2015 |
Pascal Brand <pascal.brand@st.com> |
Define TAMSG / TAMSG_RAW when CFG_TEE_CORE_TA_TRACE is undefined
Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Pascal Brand <pa
Define TAMSG / TAMSG_RAW when CFG_TEE_CORE_TA_TRACE is undefined
Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform) Signed-off-by: Pascal Brand <pascal.brand@st.com>
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| 1f7edb98 | 30-Mar-2015 |
etienne carriere <etienne.carriere@st.com> |
core: remove deprecated TA context field 'smem_size'
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Etienne CARRIERE <etienne.
core: remove deprecated TA context field 'smem_size'
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com> Tested-by: Etienne CARRIERE <etienne.carriere@st.com> Reviewed-by: Pascal BRAND <pascal.brand@st.com> Signed-off-by: Pascal Brand <pascal.brand@st.com>
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| 7583c59e | 27-Mar-2015 |
Cedric Chaumont <cedric.chaumont@st.com> |
GP Internal Core API v1.1 : add new functions, panicked IDs
- Add new functions (that will replace deprecated functions) TEE_GetObjectInfo1, TEE_RestrictObjectUsage1, TEE_CopyObjectAttributes1, TEE_
GP Internal Core API v1.1 : add new functions, panicked IDs
- Add new functions (that will replace deprecated functions) TEE_GetObjectInfo1, TEE_RestrictObjectUsage1, TEE_CopyObjectAttributes1, TEE_CloseAndDeletePersistentObject1
- Support of deprecated functions available (will be removed in future release). Note: TEE_ERROR_STORAGE_NOT_AVAILABLE case not implemented in OP-TEE core (e.g. media removal)
- Add panicked functions identifiers (debug purpose)
Signed-off-by: Cedric Chaumont <cedric.chaumont@st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Cedric Chaumont <cedric.chaumont@linaro.org> (STM boards) Tested-by: Cedric Chaumont <cedric.chaumont@linaro.org> (ARM Juno board)
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| 61ea19fd | 19-Mar-2015 |
Jens Wiklander <jens.wiklander@linaro.org> |
arm32: update types to be 64bit ready
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> |
| 7f74c64a | 01-Apr-2015 |
Pascal Brand <pascal.brand@st.com> |
Update ABI-32bits and v1.1 uint32_t changes
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform) Signed-off-by: Pascal Brand <pasc
Update ABI-32bits and v1.1 uint32_t changes
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform) Signed-off-by: Pascal Brand <pascal.brand@st.com>
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| 1f60363a | 19-Mar-2015 |
Jens Wiklander <jens.wiklander@linaro.org> |
select base types based on ILP32 and LP64 defines
* Selects base types base on the __ILP32__ and __LP64__ defines * Fixes warnings from change of base types
Signed-off-by: Jens Wiklander <jens.wikl
select base types based on ILP32 and LP64 defines
* Selects base types base on the __ILP32__ and __LP64__ defines * Fixes warnings from change of base types
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU) Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
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| db886a7f | 23-Mar-2015 |
Jerome Forissier <jerome.forissier@linaro.org> |
UART cleaning
- Rename core/include/drivers/{uart.h -> pl011.h} and core/drivers/{uart.c -> pl011.c}. Use pl011_ prefix. - Remove WITH_UART_DRV, which was used to enable pl011 on vexpress platform
UART cleaning
- Rename core/include/drivers/{uart.h -> pl011.h} and core/drivers/{uart.c -> pl011.c}. Use pl011_ prefix. - Remove WITH_UART_DRV, which was used to enable pl011 on vexpress platforms and sunxi_uart on sunxi platform. Replace it with CFG_PL011 and CFG_SUNXI_UART. - Move platform-specific (STM) code in core/arch/arm32/tee/init.c (which was guarded by #ifndef WITH_UART_DRV) to core/arch/arm32/plat-stm/tz_init.S. - Move core/arch/arm32/include/kernel/asc.h to core/arch/arm32/plat-stm.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (FVP) Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
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| 86ffc420 | 17-Mar-2015 |
SY Chiu <sy.chiu@linaro.org> |
Added new interface in PRNG Hal to inject entropy
- Added add_entropy interface in crypto_ops.prng, and expose new interface tee_prng_add_entropy() for platform vendor to inject entropy. - Injec
Added new interface in PRNG Hal to inject entropy
- Added add_entropy interface in crypto_ops.prng, and expose new interface tee_prng_add_entropy() for platform vendor to inject entropy. - Inject entropy using current timestamp every time when a session is opened or closed.
Signed-off-by: SY Chiu <sy.chiu@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: SY Chiu <sy.chiu@linaro.org> (FVP,QEMU) Tested-by: Pascal Brand <pascal.brand@linaro.org> (QEMU)
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| 177603c7 | 06-Mar-2015 |
Jens Wiklander <jens.wiklander@linaro.org> |
Define 32-bit ABI
Defines 32-bit ABI for various types passed by reference. Either by an explicit conversion to/from TEE_Param and TEE_Attribute or by changing size_t to uint32_t. Affected interface
Define 32-bit ABI
Defines 32-bit ABI for various types passed by reference. Either by an explicit conversion to/from TEE_Param and TEE_Attribute or by changing size_t to uint32_t. Affected interfaces are SVC interface and parameters passed to user TA inside tee_user_ta_enter().
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP) Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
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| 60699957 | 09-Mar-2015 |
Pascal Brand <pascal.brand@st.com> |
Check of the identity of the TA invoking a TA operation
On the following operations invoke command close cancel the one that is at the origin of the operations is checked. It could be a
Check of the identity of the TA invoking a TA operation
On the following operations invoke command close cancel the one that is at the origin of the operations is checked. It could be a TA or the core. In case of a TA, this is checked that it is the same as the one that opened the session.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (QEMU) Signed-off-by: Pascal Brand <pascal.brand@st.com>
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| 7018ae01 | 04-Mar-2015 |
SY Chiu <sy.chiu@linaro.org> |
Added Abstract Layer for PRNG
- Extended crypto_ops with a new prng_ops which handles prng operations. - Replace calls to get_rng_array() with crypto_ops.prng.read(), this enforces PRNG operations
Added Abstract Layer for PRNG
- Extended crypto_ops with a new prng_ops which handles prng operations. - Replace calls to get_rng_array() with crypto_ops.prng.read(), this enforces PRNG operations go through PRNG HAL, instead of invoking platform-dependent PRNG implementation directly. - Create a new mpa_set_random_generator() interface for mpa user to register a callback to generate random number, instead of expecting the user to provide a get_rng_array(). This enables libmpa uses crypto_ops.prng.read(). - Added a new configuration CFG_WITH_PRNG_SOFTWARE to toggle SW/HW-dependent PRNG implementation. - The SW PRNG implementation is supplied by backed cryto library(libtomcrypt). - Added a new SW PRNG 'Fortuna' to libtomcrypt. - Added a new SW PRNG 'RC4' to libtomcrypt, when Fortuna is not available due to AES and SHA256 not available, fallback to RC4. - Get rid of bad implemented SW PRNG in plat_vexpress(rng_support.c). - If CFG_WITH_PRNG_SOFTWARE is not enabled, the platform needs to supply hw_get_random_byte().
Signed-off-by: SY Chiu <sy.chiu@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform) Tested-by: SY Chiu <sy.chiu@linaro.org> (QEMU)
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| 1fd927eb | 11-Mar-2015 |
James Kung <james.kung@linaro.org> |
TEE Core File Operation Abstraction Layer
Tested-by: James Kung <james.kung@linaro.org> (QEMU platform) Signed-off-by: James Kung <james.kung@linaro.org> Reviewed-by: Jerome Forissier <jerome.foriss
TEE Core File Operation Abstraction Layer
Tested-by: James Kung <james.kung@linaro.org> (QEMU platform) Signed-off-by: James Kung <james.kung@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| ca50fe04 | 04-Feb-2015 |
Jens Wiklander <jens.wiklander@linaro.org> |
struct tee_ta_ctx: remove rw_data*
Removes rw_data and tw_data_usage elements in struct tee_ta_ctx as they are not used any longer.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewe
struct tee_ta_ctx: remove rw_data*
Removes rw_data and tw_data_usage elements in struct tee_ta_ctx as they are not used any longer.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
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| 0eff3e9b | 02-Jan-2015 |
Jens Wiklander <jens.wiklander@linaro.org> |
arm32: Adds LPAE support
Enables use of Large Physical Address Extension (LPAE) with CFG_WITH_LPAE=y
To facilitate both the old V7 and the new LPAE translation tables an abstraction layer has been
arm32: Adds LPAE support
Enables use of Large Physical Address Extension (LPAE) with CFG_WITH_LPAE=y
To facilitate both the old V7 and the new LPAE translation tables an abstraction layer has been added to avoid direct manipulations of the translation tables.
Both V7 and LPAE implementation uses TEX remapping (SCTLR.TRE = 1) and enables access flags (SCTLR.AFE = 1). This is a change in the V7 code base as those bits where 0 before. There are two reason for this change: 1."From the introduction of the Large Physical Address Extension, ARM deprecates any use of the AP[2:0] scheme for defining MMU access permissions. This deprecation applies to software for all ARMv7-A implementations, regardless of whether they include the Large Physical Address Extension." 2. With SCTLR.TRE = 1 and SCTLR.AFE = 1 V7 and LPAE implementations uses the same way of specifying access permissions and memory attributes.
Currently only supported on plat-vexpress.
Bugfix v7 config: sets NOS bit in TTBRx registers
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP Base model) Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
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| fa530828 | 03-Feb-2015 |
Pascal Brand <pascal.brand@st.com> |
Internal API extension on Cache Operations
Following extensions are introduced: - TEE_CacheClean() - TEE_CacheFlush() - TEE_CacheInvalidate()
Reviewed-by: Jerome Forissier <jerome.foris
Internal API extension on Cache Operations
Following extensions are introduced: - TEE_CacheClean() - TEE_CacheFlush() - TEE_CacheInvalidate()
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform) Signed-off-by: Pascal Brand <pascal.brand@st.com>
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| d9428c3c | 20-Jan-2015 |
SY Chiu <sy.chiu@linaro.org> |
SE API: Change configuration to be prefixed with CFG_*
Signed-off-by: SY Chiu <sy.chiu@linaro.org> Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim) |
| e4d3a4a6 | 16-Dec-2014 |
SY Chiu <sy.chiu@linaro.org> |
SE API: hide private interfaces
- Split each headers into module.h and module_priv.h, move the methods that is only used internally by SE implementation to module_priv.h, and export module_priv.
SE API: hide private interfaces
- Split each headers into module.h and module_priv.h, move the methods that is only used internally by SE implementation to module_priv.h, and export module_priv.h to rest of TEE Core - Added new include path to se_api_self_tests.c for which needs to include private headers - Split aid.c and apdu.c from iso7816.c. Originally they have to be wriiten in the same file since they share some private data structures. Now, the private data structure can be shared via private headers. - Split reader.c from manager.c for the same reason above.
Signed-off-by: SY Chiu <sy.chiu@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)
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| 197d17e7 | 12-Dec-2014 |
SY Chiu <sy.chiu@linaro.org> |
SE API: implment lubutee and svc handler
- Implemented tee_se_service - Rename tee_se_reader_handle to tee_se_reader_proxy to avoid confuse with libutee - Implemented SE API(tee_internal_se_api.h)
SE API: implment lubutee and svc handler
- Implemented tee_se_service - Rename tee_se_reader_handle to tee_se_reader_proxy to avoid confuse with libutee - Implemented SE API(tee_internal_se_api.h) in libutee - Implemented svc handler for SE API - rename protocol.[ch] to iso7816.[ch] - prefix aid_* with "tee_se_" - add an option to enable/disable se_api_self_tests
Signed-off-by: SY Chiu <sy.chiu@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)
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| e022f121 | 25-Nov-2014 |
SY Chiu <sy.chiu@linaro.org> |
SE API: Session, Protocol and Channel implementation
- Implement Session which maintains the connection between TA and a specific SE Reader - Implement ISO7816 transport layer protocol, and Channe
SE API: Session, Protocol and Channel implementation
- Implement Session which maintains the connection between TA and a specific SE Reader - Implement ISO7816 transport layer protocol, and Channel management - Implement Utilities to handle AID(ISO7816-3) and APDU(ISO7816-4) - Brunch of self tests to velidate functionality of each module
Signed-off-by: SY Chiu <sy.chiu@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)
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| f362e777 | 25-Nov-2014 |
SY Chiu <sy.chiu@linaro.org> |
SE API: SE Manager and Reader implementation
- Introduce an interface for developers to write reader driver (core/include/tee/se/reader/interface.h) - A sample reader driver implementation: PC/SC
SE API: SE Manager and Reader implementation
- Introduce an interface for developers to write reader driver (core/include/tee/se/reader/interface.h) - A sample reader driver implementation: PC/SC passthru reader (core/tee/se/reader/passthru_reader) - Currently supported machine is qemu-virt (compile with --with-pcsc-passthru) - A selftest STA is included to test the functionality of SE Reader (core/arch/arm32/sta/se_api_self_tests.c) - To enable SE API, add "WITH_SE_API := y" in your platform config
Signed-off-by: SY Chiu <sy.chiu@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)
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| 03c21dc9 | 21-Nov-2014 |
SY Chiu <sy.chiu@linaro.org> |
Introduce a Linux style initcall mechanism
To use it, simply add something like:
service_init(server_init_callback);
The callback regsitered will be invoked at the end of init_teecore(). Now we ha
Introduce a Linux style initcall mechanism
To use it, simply add something like:
service_init(server_init_callback);
The callback regsitered will be invoked at the end of init_teecore(). Now we have 2 priority service_init and driver_init. The callback regsitered in service level will be invoked first.
Signed-off-by: SY Chiu <sy.chiu@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Tested-by: SY Chiu <sy.chiu@linaro.org> (QEMU)
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| 0f2293b7 | 11-Dec-2014 |
Jerome Forissier <jerome.forissier@linaro.org> |
Add PKCS #5 v2.0 key derivation function 2 (PBKDF2)
This commit implements a crypto extension to support the key derivation function defined in section 5.2 of RFC 2898 (https://www.ietf.org/rfc/rfc2
Add PKCS #5 v2.0 key derivation function 2 (PBKDF2)
This commit implements a crypto extension to support the key derivation function defined in section 5.2 of RFC 2898 (https://www.ietf.org/rfc/rfc2898.txt), which is a re-publish of PKCS #5 v2.0. The underlying pseudorandom function is HMAC-SHA1, which is the default PRF specified in the RFC. It would be trivial to support the other HMAC functions already implemented in OP-TEE.
See documentation/extensions/crypto_pbkdf2.md for details.
Tested on PLATFORM=vexpress-qemu_virt with the test vectors from RFC 6070 (https://www.ietf.org/rfc/rfc6070.txt).
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Xiaoqiang Du <xiaoqiang.du@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
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| cdb198a7 | 04-Dec-2014 |
Jerome Forissier <jerome.forissier@linaro.org> |
Add HMAC-based extract-and-expand key derivation function (HKDF)
HKDF (http://tools.ietf.org/html/rfc5869) is a key derivation algorithm. As per the RFC:
A key derivation function (KDF) is a bas
Add HMAC-based extract-and-expand key derivation function (HKDF)
HKDF (http://tools.ietf.org/html/rfc5869) is a key derivation algorithm. As per the RFC:
A key derivation function (KDF) is a basic and essential component of cryptographic systems. Its goal is to take some source of initial keying material and derive from it one or more cryptographically strong secret keys. [...] HKDF follows the "extract-then-expand" paradigm, where the KDF logically consists of two modules. [...] The goal of the "extract" stage is to "concentrate" the possibly dispersed entropy of the input keying material into a short, but cryptographically strong, pseudorandom key. [...] The second stage "expands" the pseudorandom key to the desired length; the number and lengths of the output keys depend on the specific cryptographic algorithms for which the keys are needed.
Since HKDF is not covered by the GlobalPlatform Internal API specification v1.0/v1.1, this commit introduces extensions to the specification. More specifically: it defines new algorithms, a new object type and new object attributes. This implementation supports all the usual hash functions (MD5, SHA-1, SHA-224, SHA-256, SHA-384, SHA-512) and may produce output keys of length up to 4096 bits (currently limited only by the maximum size allowed for an object of type TEE_TYPE_GENERIC_SECRET). Aside from minor updates to object manipulation functions to support the new data, the function TEE_DeriveKey() is mostly impacted.
The file documentation/extensions/crypto_hkdf.md contains the modifications to the GP Internal API v1.0 spec in order to support HKDF.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Xiaoqiang Du <xiaoqiang.du@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform) Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
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| 8854d3c6 | 10-Dec-2014 |
Jerome Forissier <jerome.forissier@linaro.org> |
Add Concat KDF (Concatenation Key Derivation Function, NIST SP 800-56A R1)
Concat KDF is a key derivation algorithm defined in section 5.8.1 of the NIST Special Publication 800-56A Revision 1, "Reco
Add Concat KDF (Concatenation Key Derivation Function, NIST SP 800-56A R1)
Concat KDF is a key derivation algorithm defined in section 5.8.1 of the NIST Special Publication 800-56A Revision 1, "Recommendation for Pair-Wise Key Establishment Schemes Using Discrete Logarithm Cryptography" (http://csrc.nist.gov/publications/nistpubs/800-56A/SP800-56A_Revision1_Mar08-2007.pdf)
This is a TEE implementation of the function, which supports the following hash algorithms: SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512. The actual key derivation is implemented in TEE_DeriveKey() thanks to custom extensions to the GlobalPlatform API v1.0. Please refer to documentation/extensions/crypto_concat_kdf.md for details.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Xiaoqiang Du <xiaoqiang.du@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
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| 056cd73a | 07-Nov-2014 |
sunny <sunny@allwinnertech.com> |
Add plat-sunxi
Initial version support for Allwinner A80 platform. Allwinner A80 is big.little archtecture with 4*A7 + 4*A15, Support Trustzone tech and secureboot inside hardware. plat-sunxi suppor
Add plat-sunxi
Initial version support for Allwinner A80 platform. Allwinner A80 is big.little archtecture with 4*A7 + 4*A15, Support Trustzone tech and secureboot inside hardware. plat-sunxi support features: 1.Clone plat-sunxi from plat-vexpress; 2.Secure bootloader reserved 64MB secure DRAM for optee_os; 3.Support SMP secondary cpu secure stage bootup; 4.Add uart driver to core/driver/*; 5.Support GIC driver initialization. The porting work test on Optimus board, with allwinner A80 chip.
Signed-off-by: sunny <sunny@allwinnertech.com> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
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