| #
3a5e9803 |
| 07-Jun-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp1: remove SCMI0 channel index
Removes index 0 from SCMI DT binding ID macros and driver labels to synchronize with Linux kernel 5.18 that considers a single SCMI channel, see [1] and [2]
plat-stm32mp1: remove SCMI0 channel index
Removes index 0 from SCMI DT binding ID macros and driver labels to synchronize with Linux kernel 5.18 that considers a single SCMI channel, see [1] and [2].
Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-4-alexandre.torgue@foss.st.com Link: [2] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-5-alexandre.torgue@foss.st.com Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
2ceaf049 |
| 30-Jun-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: dt-bindings: stm32mp1: add IDs for STPMIC1 SCMI voltage regulators
Define the SCMI voltage domain IDs exposed by OP-TEE SCMI server on stm32mp1.
Acked-by: Jens Wiklander <jens.wiklander@linar
core: dt-bindings: stm32mp1: add IDs for STPMIC1 SCMI voltage regulators
Define the SCMI voltage domain IDs exposed by OP-TEE SCMI server on stm32mp1.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
334810f9 |
| 08-Oct-2020 |
Etienne Carriere <etienne.carriere@linaro.org> |
plat-stm32mp1: scmi: expose PWR regulators
Expose SoC PWR regulators as SCMI voltage domains to the non-secure world. They are exposed to SCMI agent scmi0 that exposes SoC resources used by non-secu
plat-stm32mp1: scmi: expose PWR regulators
Expose SoC PWR regulators as SCMI voltage domains to the non-secure world. They are exposed to SCMI agent scmi0 that exposes SoC resources used by non-secure world but controlled by secure world since RCC TZ hardening configuration.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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