stm32_i2c: driver for STM32 I2C bus

Drivers is embedded upon CFG_STM32_I2C=y.

The driver main API functions are:
stm32_i2c_init() to initialize the device driver,
stm32_i2c_mem_{write|read}() for I

stm32_i2c: driver for STM32 I2C bus

Drivers is embedded upon CFG_STM32_I2C=y.

The driver main API functions are:
stm32_i2c_init() to initialize the device driver,
stm32_i2c_mem_{write|read}() for I2C memory mode transfer,
stm32_i2c_master_{transmit|receive}() for stream transfer.

2 helpers:
stm32_i2c_is_device_ready() checks the hardware I2C link,
stm32_i2c_get_setup_from_fdt() fills the I2C initialization
structure from the content found in the DT.

I2C driver instances do not register themselves to the PM
framework. Bus owner is responsible for calling the
stm32_i2c_{suspend|resume}() APIs when the owner device
executes a PM sequence.

stm32_i2c driver is dual licensed GPL-2.0/BSD-3-Clause.
The conversion algorithm for converting device tree bindings
timing information into STM32 I2C timings configuration
register is shared with other packages (Linux kernel, Arm
Trusted Firmware-A, U-Boot).

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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stm32_bsec: OTP driver for stm32mp platforms

BSEC is a one time programmable (OTP) memory interface for stm32mp
SoCs. OTPs are grouped into 32bit words identified by a incremental ID
starting from 0

stm32_bsec: OTP driver for stm32mp platforms

BSEC is a one time programmable (OTP) memory interface for stm32mp
SoCs. OTPs are grouped into 32bit words identified by a incremental ID
starting from 0. Shadowed OTPs are loaded in a volatile memory yet
used as OTP values by the software.

The platform shall implement stm32mp_get_bsec_static_cfg() to
provide BSEC driver some information as the BSEC memory size and
its lower/upper threshold ID that split non-secure from secure OTPs.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Christophe Montaud <christophe.montaud@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32_gpio: driver for GPIO and pin control

Driver is embedded upon CFG_STM32_GPIO=y.

STM32 GPIO driver API main functions:
- stm32_gpio_set_output_level() sets target output GPIO level,
- stm32_gp

stm32_gpio: driver for GPIO and pin control

Driver is embedded upon CFG_STM32_GPIO=y.

STM32 GPIO driver API main functions:
- stm32_gpio_set_output_level() sets target output GPIO level,
- stm32_gpio_get_input_level() returns target input GPIO level,
- stm32_pinctrl_load_active_cfg() loads interface pin mux active state,
- stm32_pinctrl_load_standby_cfg() loads interface pin mux standby state,
- stm32_pinctrl_fdt_get_pinctrl() save pin configuration from DT content,
- stm32_gpio_set_secure_cfg() sets secure state for target GPIO/pin mux.

GPIO driver does not register to PM framework. It is the GPIO/pin owner
responsibility to call stm32_pinctrl_load_{active|standby}_cfg() on
peripherals power state transitions.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32_etzpc: STM32 Extended TrustZone Protection Controller

ETZPC is a hardware instance that control access permissions to
some stm32mp SoC peripheral interfaces and internal memories.

This change

stm32_etzpc: STM32 Extended TrustZone Protection Controller

ETZPC is a hardware instance that control access permissions to
some stm32mp SoC peripheral interfaces and internal memories.

This change introduce the stm32_etzpc driver. It is embedded upon
build directive CFG_STM32_ETZPC=y.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Mathieu BELOU <mathieu.belou@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: stm32_uart driver

Used by platform stm32mp1.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <je

core: stm32_uart driver

Used by platform stm32mp1.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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Remove support for Allwinner A80 platform (plat-sunxi)

It has been almost three years since we have heard about plat-sunxi
(no new contributions, no patch ack'ed or tested, no feedback at
release ti

Remove support for Allwinner A80 platform (plat-sunxi)

It has been almost three years since we have heard about plat-sunxi
(no new contributions, no patch ack'ed or tested, no feedback at
release time). Therefore, remove support for this platform.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
CC: Sun Yangbang <sunny@allwinnertech.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-marvell: Add initial support for ARMADA3700

Only test 64bit mode with default configuration

1. Build command
make PLATFORM=marvell-armada3700
2. Pass xtest

Signed-off-by: wangwen <wangwen

plat-marvell: Add initial support for ARMADA3700

Only test 64bit mode with default configuration

1. Build command
make PLATFORM=marvell-armada3700
2. Pass xtest

Signed-off-by: wangwen <wangwen@marvell.comi>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Kevin Peng <kevinp@marvell.com>

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core: drivers: add imx wdog support

Introducing the wdog support is for psci reset usage.
To i.MX6/7, when `reboot`, need wdog to trigger soc reset
or send out signal to pmic through wdog pin to tri

core: drivers: add imx wdog support

Introducing the wdog support is for psci reset usage.
To i.MX6/7, when `reboot`, need wdog to trigger soc reset
or send out signal to pmic through wdog pin to trigger pmic reset.

In linux device tree, there is a "fsl,ext-reset-output" property, this
driver is to check whether the wdog node contains the property or not,
then decide how to trigger reset.

We still rely on normal world to initialize wdog and configure pinmux
when need to trigger pmic reset.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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TUI: remove frame buffer

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

TUI: remove ps2mouse

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

TUI: remove clcd pl111

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

TUI: remove PL050

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-sam: Add support for Atmel-Microchip SAMA5D2-XULT board

Add basic support to get op-tee to run on SAMA5D2-XULT board.

The SoC is based on single core ARM Cortex-A5 and supports:
ARM TrustZone

plat-sam: Add support for Atmel-Microchip SAMA5D2-XULT board

Add basic support to get op-tee to run on SAMA5D2-XULT board.

The SoC is based on single core ARM Cortex-A5 and supports:
ARM TrustZone with support for configuring memory/peripherals as secure
Secure RTC
Secure boot
On-the-fly encryption/decryption of DDR bus
Tamper protection

Link: http://www.atmel.com/Images/Atmel-11267-32-bit-Cortex-A5-Microcontroller-SAMA5D2_Datasheet.pdf
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: add snvs srtc support

Introduce i.MX SNVS SRTC support. The SRTC works with 32.768KHz.
The SRTC is in SNVS_LP domain. The SNVS_LP is a data storage
subsystem with enhanced security capabili

drivers: add snvs srtc support

Introduce i.MX SNVS SRTC support. The SRTC works with 32.768KHz.
The SRTC is in SNVS_LP domain. The SNVS_LP is a data storage
subsystem with enhanced security capabilities. Its purpose is to store
and protect system data, regardless of the main system power state.
SNVS_LP is in the always-powered-up domain, which is a separate power
domain with its own power supply. When the chip power supply domain
loses power, SNVS_LP continues to operate normally.

Since OP-TEE does not care about calendar time, there is no need
to update calendar time, we only need to read the counter and
get out the time.

The plat_prng_add_jitter_entropy is reused from tee_time_arm_cntpct.c.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: tzc380: add tzc380 driver

Add tzc380 driver support.

The usage:
Use tzc_init(vaddr_t base) to get the tzc380 configuration.
Use tzc_configure_region to configure the memory region,
such as

drivers: tzc380: add tzc380 driver

Add tzc380 driver support.

The usage:
Use tzc_init(vaddr_t base) to get the tzc380 configuration.
Use tzc_configure_region to configure the memory region,
such as "tzc_configure_region(5, 0x4e000000,
TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_32M) | TZC_ATTR_REGION_EN_MASK |
TZC_ATTR_SP_S_RW);"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: move stih UART driver to the drivers/ directory

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

drivers: Add TRNG driver for DRA7

Add driver for the True Random Number Generator (TRNG) available
on DRA7xx platforms.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Joakim Bech <joakim.

drivers: Add TRNG driver for DRA7

Add driver for the True Random Number Generator (TRNG) available
on DRA7xx platforms.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: add SCIF driver

SCIF stands for "Serial Communication Interface with FIFO".
It is an UART device used on different Renesas SoCs.

Signed-off-by: Volodymyr Babchuk <volodymyr.babchuk@globall

drivers: add SCIF driver

SCIF stands for "Serial Communication Interface with FIFO".
It is an UART device used on different Renesas SoCs.

Signed-off-by: Volodymyr Babchuk <volodymyr.babchuk@globallogic.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: add tzc400 driver

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add ps2mouse driver

Adds a PS/2 mouse driver that uses serial abstract driver for
communication with the mouse.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David

core: add ps2mouse driver

Adds a PS/2 mouse driver that uses serial abstract driver for
communication with the mouse.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add pl050 (KMI) driver

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add pl111 (LCD) driver

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add generic framebuffer driver

Adds a generic framebuffer driver. Currently only supports framebuffers
configured for 24BPP.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Review

core: add generic framebuffer driver

Adds a generic framebuffer driver. Currently only supports framebuffers
configured for 24BPP.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: add Hi16xx RNG driver

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: etienne carriere <etienne.carriere@linaro.

drivers: add Hi16xx RNG driver

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: etienne carriere <etienne.carriere@linaro.org>

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Add UART driver for Hisilicon Hi16xx

Applies to SoCs in the Hi16xx family, and to Phosphor V660 a.k.a. hip05
(the CPU on the Hisilicon D02 development board).

Signed-off-by: Jerome Forissier <jerom

Add UART driver for Hisilicon Hi16xx

Applies to SoCs in the Hi16xx family, and to Phosphor V660 a.k.a. hip05
(the CPU on the Hisilicon D02 development board).

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>

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