core: interrupt: rename .add handler to .configure

Rename field add of struct itr_ops to configure for consistency
since that handler is used the configure the interrupt. Update
existing interrupt d

core: interrupt: rename .add handler to .configure

Rename field add of struct itr_ops to configure for consistency
since that handler is used the configure the interrupt. Update
existing interrupt drivers accordingly.

By the way fix inline comment spelling typo (s/contrainsts/constraints/).

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: plic: Fix parameter type of plic_op_raise_sgi()

The commit ec740b9fe95e ("core: interrupt_raise_sgi() updates") changes
the cpu_mask parameter to a uint32_t. Apply this change onto
plic_op_

drivers: plic: Fix parameter type of plic_op_raise_sgi()

The commit ec740b9fe95e ("core: interrupt_raise_sgi() updates") changes
the cpu_mask parameter to a uint32_t. Apply this change onto
plic_op_raise_sgi().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: plic: Ignore interrupt source ID 0

According to RISC-V PLIC specification, interrupt ID 0 is reserved to
mean "no interrupt". Therefore, we should ignore it.

Signed-off-by: Alvin Chang <al

drivers: plic: Ignore interrupt source ID 0

According to RISC-V PLIC specification, interrupt ID 0 is reserved to
mean "no interrupt". Therefore, we should ignore it.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: move to interrupt_call_handlers()

Removes itr_handle() in favor to interrupt_call_handlers(). This
changes updates all implemented main interrupt controller drivers that
are the GIC driver,

drivers: move to interrupt_call_handlers()

Removes itr_handle() in favor to interrupt_call_handlers(). This
changes updates all implemented main interrupt controller drivers that
are the GIC driver, the HFIC driver and Atmel SAIC driver.

Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: plic: Implement mask/unmask operations

Implement mask/unmask operations for PLIC, otherwise OP-TEE panics
during boot process due to failure of itr_chip_is_valid().

Signed-off-by: Alvin Ch

drivers: plic: Implement mask/unmask operations

Implement mask/unmask operations for PLIC, otherwise OP-TEE panics
during boot process due to failure of itr_chip_is_valid().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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drivers: plic: Maintain controller data in driver source file

To align the design from other architecture, we move the interrupt
controller data instance from platform source file to driver source
f

drivers: plic: Maintain controller data in driver source file

To align the design from other architecture, we move the interrupt
controller data instance from platform source file to driver source
file. With this change, the PLIC initialization functions no more get
the controller data as input argument. Platforms do not need to care
about the interrupt controller data instance.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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drivers: plic: Refine interrupt targets from hartid to context

The PLIC specification says the interrupt targets are usually hart
contexts, where a hart context is a given privilege mode on a given

drivers: plic: Refine interrupt targets from hartid to context

The PLIC specification says the interrupt targets are usually hart
contexts, where a hart context is a given privilege mode on a given
hart. Therefore, PLIC driver should not only consider the HART ID, but
also current privilege mode. Refine it by introducing the function
called plic_get_context(), which translates the current HART ID into the
PLIC context ID. We assume that each hart has M-mode and S-mode,
therefore M-mode occupies even-numbered context ID, while S-mode
occupies odd-numbered context ID. The translation can be extended by
parsing device tree, submitted in future commits.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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riscv: driver: implement platform-level interrupt controller (PLIC) driver

An initial implementation of RISC-V PLIC driver conforming
to the specification. CFG_RISCV_PLIC flag allows building it
or

riscv: driver: implement platform-level interrupt controller (PLIC) driver

An initial implementation of RISC-V PLIC driver conforming
to the specification. CFG_RISCV_PLIC flag allows building it
or not for platforms with custom PLIC IP.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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