crypto: stm32: fix stm32_saes CTR mode on small input buffers

Fix missing cast when saving pre-computed masks in STM32 SAES driver
CTR implementation when several small input data is provided to
the

crypto: stm32: fix stm32_saes CTR mode on small input buffers

Fix missing cast when saving pre-computed masks in STM32 SAES driver
CTR implementation when several small input data is provided to
the update handler.

The issue is revealed by xtest regression_4017 when run with at least
level 12, e.g. "xtest -l 15 regression_4017".

Fixes: 4320f5cf30c5 ("crypto: stm32: SAES cipher support")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: use fdt_reg_info()

Use fdt_reg_info() instead of fdt_reg_base_address() and fdt_reg_size()
to optimize look up in the DT due to finding parent node.

Signed-off-by: Etienne Carriere <etienn

drivers: use fdt_reg_info()

Use fdt_reg_info() instead of fdt_reg_base_address() and fdt_reg_size()
to optimize look up in the DT due to finding parent node.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: stm32: fix SAES driver set_field_u32 usage

set_field_u32() is a function that allows you to change a specific bit
in a register by using a mask. The function returns the full value

drivers: crypto: stm32: fix SAES driver set_field_u32 usage

set_field_u32() is a function that allows you to change a specific bit
in a register by using a mask. The function returns the full value of
the register, which means that the use of bitwise OR here is a mistake.
The current code works here only because the modified registers are
initialized. Moreover, I've reverted a commit as there is no
need to shift the value as the function already does it.

Fix the usage of the function in the SAES driver by replacing
bitwise OR assignments with simple assignments.

Fixes: c83a542f3734 ("drivers: crypto: stm32: fix SAES key selection")
Fixes: 4320f5cf30c5 ("crypto: stm32: SAES cipher support")
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32_saes: SAES depends on RNG clock

Fixes missing dependency of SAES device on RNG clock.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Thomas Bou

drivers: crypto: stm32_saes: SAES depends on RNG clock

Fixes missing dependency of SAES device on RNG clock.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: crypto: stm32_saes: add PM to SAES driver

Add power management support to the SAES driver through suspend/resume
callbacks.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
S

drivers: crypto: stm32_saes: add PM to SAES driver

Add power management support to the SAES driver through suspend/resume
callbacks.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: crypto: stm32: clean function references

Remove useless & operator in function references of stm32 crypto drivers.
No functional changes.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss

drivers: crypto: stm32: clean function references

Remove useless & operator in function references of stm32 crypto drivers.
No functional changes.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32: fix SAES key selection

Correction selection of key in STM32 SAES driver that missed a
left bit shift operation. The bug was not experienced before as
current platform tests i

drivers: crypto: stm32: fix SAES key selection

Correction selection of key in STM32 SAES driver that missed a
left bit shift operation. The bug was not experienced before as
current platform tests involve only the software key selection
(_SAES_CR_KEYSEL_SOFT) which value is 0 and matches the SoC default
key selection register value.

Fixes: 4320f5cf30c5 ("crypto: stm32: SAES cipher support")
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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crypto: stm32: fix SAES reset at probe time

Uses SAES internal reset sequence only when external reset controller
is not available. This change fixes a non-systematic SAES error
seen when SAES inter

crypto: stm32: fix SAES reset at probe time

Uses SAES internal reset sequence only when external reset controller
is not available. This change fixes a non-systematic SAES error
seen when SAES internal reset is triggered right after external reset
sequence. Whereas a fix could be to add a delay between external reset
and internal reset sequences, this change simplifies the sequence as
internal reset sequence is not needed when SAES instance is reset using
its external reset controller.

Fixes: 4320f5cf30c5 ("crypto: stm32: SAES cipher support")
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_saes: redefine huk_subkey_derive()

We set huk_subkey_derive() as a weak function and we define it in SAES
driver to be able to use SAES IP to make a secure key derivation from
the SAE

drivers: stm32_saes: redefine huk_subkey_derive()

We set huk_subkey_derive() as a weak function and we define it in SAES
driver to be able to use SAES IP to make a secure key derivation from
the SAES only accessible SOC unique secret key.

We use the Key Derivation function (KDF) in counter mode defined in [1]
using as the PRF (pseudo random function) the PRF(AES-CMAC).
PRF(AES-CMAC) is hardware accelerated by SAES, and use the secure DHUK
(derived hardware unique key) only readable by the SAES IP.

Link: https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-108r1.pdf [1]
Co-developed-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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crypto: stm32: SAES cipher support

Add SAES HW driver, and update OP-TEE cipher hooks to be able to use
SAES or CRYP for cipher algorithms.
SAES and CRYP cannot be enabled at the same time in OP-TEE

crypto: stm32: SAES cipher support

Add SAES HW driver, and update OP-TEE cipher hooks to be able to use
SAES or CRYP for cipher algorithms.
SAES and CRYP cannot be enabled at the same time in OP-TEE.

Co-developed-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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